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參數資料
| 型號： | HD74AC107 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Dual JK Flip-Flop (with Separate Clear and Clock)(雙JK觸發器(帶獨立清除和時鐘)) |
| 中文描述： | 雙JK觸發器（具有獨立清晰，時鐘）（雙JK觸發器（帶獨立清除和時鐘）） |
| 文件頁數： | 1/10頁 |
| 文件大小： | 57K |
| 代理商： | HD74AC107 |
HD74AC107/HD74ACT107
Dual JK Flip-Flop (with Separate Clear and Clock)
Description
The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop.
Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the
coupling transistors which connect the master and slave sections. The sequence of operation is as follows:
1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs;
4) transfer information from master to slave.
Features
Outputs Source/Sink 24 mA
HD74ACT107 has TTL-Compatible Inputs
Pin Arrangement
1
2
3
4
5
6
7
J
1
Q
1
Q
1
K
1
Q
2
Q
2
GND
V
CC
C
D1
CP
1
K
2
C
D2
CP
2
J
2
14
13
12
11
10
9
8
(Top view)
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| HD74ACT112 | Dual JK Negative Edge-Triggered Flip-Flop |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HD74AC107/HD74ACT107 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| HD74AC107FP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FLIP-FLOP|DUAL|J/K TYPE|AC-CMOS|SOP|14PIN|PLASTIC |
| HD74AC107FPEL | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:Dual JK Flip-Flop (with Separate Clear and Clock) |
| HD74AC107P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| HD74AC107RP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FLIP-FLOP|DUAL|J/K TYPE|AC-CMOS|SOP|14PIN|PLASTIC |
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