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參數資料
| 型號： | HD74HC93 |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-bit Binary Counter |
| 中文描述： | 4位二進制計數器 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 55K |
| 代理商： | HD74HC93 |
HD74HC93
4-bit Binary Counter
Description
The HD74HC93 is a 4-bit ripple type counter consisting of four master/slave flip-flops that are internally
connected to provide separate divide-by-two and divide-by-eight sections. Each section has a separate
clock input which initiates state changes of the counter on the high-to-low clock transition. State changes
of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output
signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated
with the clock of the HD74HC93. Q
A
is the output of the divide-by-two section; Q
B
, Q
C
, and Q
D
are the
binary outputs of the divide-by-eight section.
A gated AND asynchronous reset is provided which resets all the flip-flops.
Because the output from the divide-by-two section is not internally connected to the succeeding stages, the
devices may be operated in various counting modes:
1. A 4-bit rippl counter – The Q
A
output must be externally connected to the clock B input. The input
count pulses are applied to the clock A inputl. Simultaneous divisions of 2, 4, 8 and 16 are performed at
the Q
A
, Q
B
, Q
C
and Q
D
outputs.
2. A 3-bit ripple counter – The input count pulses are applied to the clock B input. Simultaneous
frequency divisions of 2, 4 and 8 are available at the Q
B
, Q
C
and Q
D
outputs. Independent use of the
first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter.
Features
High Speed Operation: t
pd
(A to Q
A
) = 13 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 μA max
Low Quiescent Supply Current: I
CC
(static) = 4 μA max (Ta = 25°C)
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