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參數資料
| 型號： | HDMP-0482 |
| 英文描述： | Octal Cell Port Bypass Circuit with CDR and Data Valid Detection |
| 中文描述： | 八路細胞端口旁路電路CDR和數據有效檢測 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 149K |
| 代理商： | HDMP-0482 |
Agilent HDMP-0482
Octal Cell Port Bypass Circuit
with CDR and Data Valid Detection
Data Sheet
Description
The HDMP-0482 is an Octal Cell
Port Bypass Circuit (PBC) with
Clock and Data Recovery (CDR)
and data valid detection capabil-
ity included. This device mini-
mizes part count, cost and jitter
accumulation while repeating
incoming signals. Port Bypass
Circuits are used in hard disk
arrays constructed in Fibre
Channel Arbitrated Loop
(FC-AL) configurations. By using
Port Bypass Circuits, hard disks
may be pulled out or swapped
while other disks in the array are
available to the system.
A Port Bypass Circuit (PBC)
consists of multiple 2:1 multiplex-
ers daisy chained along with a
CDR. Each port has two modes of
operation: “disk in loop” and
“disk bypassed”. When the “disk
in loop” mode is selected, the loop
goes into and out of the disk drive
at that port. For example, data
goes from the HDMP-0482’s
TO_NODE[n]
±
differential output
pins to the Disk Drive Transceiver
IC’s (e.g. an HDMP-1636A) Rx
±
differential input pins. Data from
the Disk Drive Transceiver IC’s
Tx
±
differential outputs goes to
Features
Supports 1.0625 GBd fibre channel
operation
Supports 1.25 GBd Gigabit Ethernet
(GE) operation
Octal cell PBC/CDR in one package
CDR location determined by choice
of cable input/output
Amplitude valid detection on
FM_NODE[7] input
Data valid detection on
FM_NODE[0] input
– Run length violation detection
– Comma detection
– Configurable for both single-
frame and multi-frame detection
Equalizers on all inputs
High speed LVPECL I/O
Buffered Line Logic (BLL) outputs
(no external bias resistors
required)
1.09 W typical power at Vcc=3.3V
64 Pin, 14 mm, low cost plastic QFP
package
Applications
RAID, JBOD, BTS cabinets
Four 2:1 muxes
Four 1:2 buffers
1 = > N gigabit serial buffer
N = > 1 gigabit serial mux
the HDMP-0482’s FM_NODE[n]
±
differential input pins. When the
“disk bypassed” mode is selected,
the disk drive is either absent or
non-functional and the loop
bypasses the hard disk.
The “disk bypassed” mode is
enabled by pulling the BYPASS[n]-
pin low. Leave BYPASS[n]-
floating to enable the “disk in
loop” mode. HDMP-0482’s may be
cascaded with other members of
the HDMP-04XX/HDMP-05XX
family through the FM_NODE and
TO_NODE pins to accommodate
any number of hard disks. The
unused cells in this PBC may be
bypassed by using pulldown
resistors on the BYPASS[n]- pins
for these cells.
An HDMP-0482 may also be used
as eight 1:1 buffers, one with a
CDR and seven without. For
example, an HDMP-0482 may be
placed in front of a CMOS ASIC
to clean the jitter of the outgoing
signal (CDR path) and to better
read the incoming signal (non-
CDR path). In addition, the
HDMP-0482 may be configured as
four 2:1 multiplexers or as four
1:2 buffers.
HDMP-0482
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions
be taken in the handling and assembly of this component to prevent damage and/or
degradation which may be induced by electrostatic discharge (ESD).
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