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參數資料
| 型號： | HI1166AIL |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 250 MSPS, Flash A/D Converter |
| 中文描述： | 2-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, CQCC68 |
| 封裝： | CERAMIC, LCC-68 |
| 文件頁數： | 12/12頁 |
| 文件大小： | 125K |
| 代理商： | HI1166AIL |
12
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
HI1166
Ceramic Leadless Chip Carrier Packages (CLCC)
D
j
x 45
o
D3
B
h x 45
o
A
A1
E
L
L3
e
B3
L1
D2
D1
e
1
E2
E1
L2
PLANE 2
PLANE 1
E3
B2
0.010
E H
S
S
0.010
E F
S
S
-E-
0.007
E F
M
S H S
B1
-H-
-F-
J68.A
68 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.067
0.087
1.70
2.20
6, 7
A1
0.058
0.072
1.47
1.83
-
B
-
-
-
-
-
B1
0.033
0.039
0.85
0.99
2, 4
B3
0.006
0.022
0.15
0.56
-
D
0.940
0.965
23.88
24.51
-
D1
0.800 BSC
20.32 BSC
-
D2
0.400 BSC
10.16 BSC
-
D3
0.616
0.632
15.65
16.05
2
E
0.940
0.965
23.88
24.51
-
E1
0.800 BSC
20.32 BSC
-
E2
0.400 BSC
10.16 BSC
-
E3
0.616
0.632
15.65
16.05
2
e
0.050 BSC
1.27 BSC
-
e1
0.015
-
0.38
-
2
j
0.040 Ref
1.00 Ref
5
L
0.045
0.055
1.14
1.40
-
L1
0.045
0.055
1.14
1.40
-
L2
0.075
0.095
1.91
2.41
-
L3
0.003
0.015
0.08
0.38
-
ND
17
17
3
NE
17
17
3
N
68
68
3
Rev. 0 5/18/94
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HI1166-EV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 250 MSPS, Flash A/D Converter |
| HI1166Y | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit 250 MSPS Flash A/D Converter |
| HI117 | 制造商:HSMC 制造商全稱:HSMC 功能描述:PNP EPITAXIAL PLANAR TRANSISTOR |
| HI1171 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8位， 40個中型項目，高速D / A轉換器 |
| HI1171_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 40 MSPS, High Speed D/A Converter |
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