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參數資料
| 型號： | HI5812JIJ |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24 |
| 封裝： | CERDIP-24 |
| 文件頁數： | 3/13頁 |
| 文件大小： | 427K |
| 代理商： | HI5812JIJ |
6-1791
Absolute Maximum Ratings
Thermal Information
Supply Voltage
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . .(V
SS
-0.5V) < V
DD
< +6.5V
V
AA
+ to V
AA
-. . . . . . . . . . . . . . . . . . . .(V
SS
-0.5V) to (V
SS
+6.5V)
V
AA
+ to V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
0.3V
Analog and Reference Inputs
V
IN
, V
REF
+, V
REF
-. . . . . . . . . (V
SS
-0.3V) < V
INA
< (V
DD
+0.3V)
Digital I/O Pins . . . . . . . . . . . . . . (V
SS
-0.3V) < VI/O < (V
DD
+0.3V)
Operating Conditions
Temperature Range
PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
CERDIP Package . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
ο
C to 150
o
C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
θ
JA
(
o
C/W)
60
80
75
θ
JC
(
o
C/W)
12
N/A
N/A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
DD
= V
AA
+ = 5V, V
REF
+ = +4.608V, V
SS
= V
AA
- = V
REF
- = GND, CLK = External 750kHz,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
25
o
C
-
40
o
C TO 85
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
ACCURACY
Resolution
12
-
-
12
-
Bits
Integral Linearity Error, INL
(End Point)
J
-
-
±
1.5
-
±
1.5
LSB
K
-
-
±
1.0
-
±
1.0
LSB
Differential Linearity Error, DNL
J
-
-
±
2.0
-
±
2.0
LSB
K
-
-
±
1.0
-
±
1.0
LSB
Gain Error, FSE
(Adjustable to Zero)
J
-
-
±
3.0
-
±
3.0
LSB
K
-
-
±
2.5
-
±
2.5
LSB
Offset Error, V
OS
(Adjustable to Zero)
J
-
-
±
2.0
-
±
2.0
LSB
K
-
-
±
1.0
-
±
1.0
LSB
Power Supply Rejection, PSRR
Offset Error PSRR
Gain Error PSRR
V
REF
= 4V
V
DD
=
V
AA
+ = 5V
±
5%
V
DD
=
V
AA
+ = 5V
±
5%
0.1
0.1
±
0.5
±
0.5
±
0.5
±
0.5
LSB
LSB
DYNAMIC CHARACTERISTICS
Signal to Noise Ratio, SINAD
RMS Signal
RMS Noise + Distortion
J
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
=Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
f
S
= Internal Clock, f
IN
= 1kHz
f
S
= 750kHz, f
IN
= 1kHz
-
68.8
69.2
-
-
-
dB
dB
K
-
71.0
71.5
-
-
-
dB
dB
Signal to Noise Ratio, SNR
RMS Signal
RMS Noise
J
-
70.5
71.1
-
-
-
dB
dB
K
-
71.5
72.1
-
-
-
dB
dB
Total Harmonic Distortion, THD
J
-
-73.9
-73.8
-
-
-
dBc
dBc
K
-80.3
-79.0
-
-
-
dBc
dBc
Spurious Free Dynamic Range,
SFDR
J
-
-75.4
-75.1
-
-
-
dB
dB
K
-
-80.9
-79.6
-
-
-
dB
dB
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