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參數(shù)資料
| 型號： | HIP0063AB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 功率晶體管 |
| 英文描述： | Hex Low Side MOSFET Driver with Serial or Parallel Interface and Diagnostic Fault Control |
| 中文描述： | 0.0044 A 6 CHANNEL, BUF OR INV BASED MOSFET DRIVER, PDSO28 |
| 封裝： | PLASTIC, MS-013-AE, SOIC-28 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 61K |
| 代理商： | HIP0063AB |
2
HIP0063
FIGURE 1. TYPICAL APPLICATION CIRCUIT FOR THE HIP0063 SHOWING HOW THE GATE DRIVE OUTPUT AND DRAIN MONITOR
INPUT CONTROLS TWO HIP0061 THREE FET ARRAYS
FIGURE 2. SPI DATA AND CLOCK TIMING DIAGRAM. SERIAL COMMUNICATION IS INITIATED WHEN CS GOES LOW AND SCK
IS LOW. 8 OR 16 BITS OF DATA IS CLOCKED INTO SI ON THE LEADING EDGE OF SCK. DATA IS CLOCKED OUT OF
SO ON THE TRAIL EDGE OF SCK. WHEN CS GOES HIGH, DATA IS LATCHED TO CONTROL EACH CHANNEL
DRAIN MONITOR
GATE DRIVER
DATA
LATCH
DRIVE CONTROL
CHANNEL #0
5V
GND
P
V
CC
PI0
PI1
PI2
PI3
PI4
PI5
V
PWR
14V
2 - HIP0061
OR EQUIVALENT
HARDWARE GENERATED OR CUSTOM LOGIC
SOURCED PWM CONTROL SIGNAL INPUTS
POR, TIMING OSC,
BAND GAP REF.,
OVER-VOLT. DET.
D5
G5
S0
SI
SCK
CS
HLOS (SEL)
HPW01
HPW45
HIP0063
D4
G4
D3
G3
D2
G2
D1
G1
D0
G0
V
PWR
(V
BATT
)
14V
DRAIN MONITOR
GATE DRIVER
DATA
LATCH
DRIVE CONTROL
CHANNEL #1
DRAIN MONITOR
GATE DRIVER
DATA
LATCH
DRIVE CONTROL
CHANNEL #2
DRAIN MONITOR
GATE DRIVER
DATA
LATCH
DRIVE CONTROL
CHANNEL #3
DRAIN MONITOR
GATE DRIVER
DATA
LATCH
DRIVE CONTROL
CHANNEL #4
DRAIN MONITOR
GATE DRIVER
DATA
LATCH
DRIVE CONTROL
CHANNEL #5
PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL
PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL
PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL
PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL
PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL
PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL
HLOS
SPI
CS
SCK
(CPOL = 0, CPHA = 1)
INTERNAL STROBE FOR DATA CAPTURE
MSB
6
5
4
3
2
1
LSB
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