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參數資料
| 型號： | HIP6020A |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Advanced Dual PWM and Dual Linear Power Controller |
| 中文描述： | 先進的雙PWM和線性雙電源控制器 |
| 文件頁數： | 11/16頁 |
| 文件大小： | 192K |
| 代理商： | HIP6020A |
4-11
PWM1 Controller Feedback Compensation
Both PWM controllers use voltage-mode control for output
regulation. This section highlights the design consideration
for a voltage-mode controller requiring external
compensation. Apply these methods and considerations
only to the synchronous PWM controller. The considerations
for the standard PWM controller are presented separately.
Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT) for
PWM1. The error amplifier output (V
E/A
) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V
IN
at the PHASE node.
The PWM wave is smoothed by the output filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain, given by V
IN
/V
OSC
, and shaped by the output filter, with
a double pole break frequency at F
LC
and a zero at F
ESR
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6020A) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f
0dB
) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f
0dB
and 180
degrees
.
The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 11. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
Figure 12 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 12. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
V
OUT1
Q1
L
OUT1
Q2
Q3
Q4
C
SS
+12V
C
VCC
VCC
OCSET2
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
C
OUT1
CR1
HIP6020A
C
IN
C
OUT2
V
OUT2
V
OUT3
+5V
IN
SS
PGND
LGATE1
UGATE1
PHASE1
DRIVE3
PHASE2
KEY
L
OUT2
GND
UGATE2
OCSET1
R
OCSET1
R
OCSET2
C
OCSET1
C
OCSET2
L
V
OUT4
DRIVE4
+3.3V
IN
L
IN
CR2
Q5
C
OUT3
C
OUT4
L
L
L
F
LC
L
O
2
π
C
O
×
×
---------------------------------------
=
F
ESR
O
-----------------------------------------
=
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
COMP
+
-
DRIVER
(PARASITIC)
Z
FB
+
-
DACOUT
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
HIP6020A
Z
IN
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
Z
IN
F
Z1
-----------------------------------
=
F
Z2
R3
)
C3
×
------------------------+
=
F
P1
2
π
R
2
----------+
×
×
------------------------------------------------------
=
F
P2
-----------------------------------
=
HIP6020A
相關PDF資料 |
PDF描述 |
|---|---|
| HIP6020ACB | Advanced Dual PWM and Dual Linear Power Controller |
| HIP6020EVAL1 | Advanced Dual PWM and Dual Linear Power Controller |
| HIP6020 | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP6020CB | Advanced Dual PWM and Dual Linear Power Controller |
| HIP6301VCBZ-T | 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HIP6020A_01 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Advanced Dual PWM and Dual Linear Power Controller |
| HIP6020ACB | 制造商:Intersil Corporation 功能描述: |
| HIP6020ACB WAF | 制造商:Harris Corporation 功能描述: |
| HIP6020ACB-T | 制造商:Rochester Electronics LLC 功能描述:DUAL PWM AND 2 LINEAR CONTROLLER W/O VID=11111 SHUTDOWN - Tape and Reel |
| HIP6020CB | 制造商:Rochester Electronics LLC 功能描述:DUAL PWM AND 2 LINEAR CONTROLLER - Bulk |
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