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參數(shù)資料
| 型號： | HIP6020A |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Advanced Dual PWM and Dual Linear Power Controller |
| 中文描述： | 先進的雙PWM和線性雙電源控制器 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 192K |
| 代理商： | HIP6020A |
4-16
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil Ltd.
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
HIP6020A
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbolsaredefinedinthe“MOSeriesSymbolList”inSection2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M
-
1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
0.25(0.010)
B
M
M
α
M28.3
(JEDEC MS-013-AE ISSUE C
)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
e
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
28
28
7
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP6020ACB | Advanced Dual PWM and Dual Linear Power Controller |
| HIP6020EVAL1 | Advanced Dual PWM and Dual Linear Power Controller |
| HIP6020 | FPGA - 100000 SYSTEM GATE 2.5 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP6020CB | Advanced Dual PWM and Dual Linear Power Controller |
| HIP6301VCBZ-T | 100000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP6020A_01 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Advanced Dual PWM and Dual Linear Power Controller |
| HIP6020ACB | 制造商:Intersil Corporation 功能描述: |
| HIP6020ACB WAF | 制造商:Harris Corporation 功能描述: |
| HIP6020ACB-T | 制造商:Rochester Electronics LLC 功能描述:DUAL PWM AND 2 LINEAR CONTROLLER W/O VID=11111 SHUTDOWN - Tape and Reel |
| HIP6020CB | 制造商:Rochester Electronics LLC 功能描述:DUAL PWM AND 2 LINEAR CONTROLLER - Bulk |
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