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參數資料
| 型號： | HIP6503EVAL1 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Multiple Linear Power Controller with ACPI Control Interface |
| 中文描述： | 多重線性電源控制器ACPI控制接口 |
| 文件頁數： | 12/14頁 |
| 文件大小： | 151K |
| 代理商： | HIP6503EVAL1 |
12
Input Capacitors Selection
The input capacitors for an HIP6503 application have to
have a sufficiently low ESR as to not allow the input voltage
to dip excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the HIP6503’s regulation levels could have as a
result a brisk transfer of energy from the input capacitors to
the supplied outputs. At the transition between active and
sleep states, this phenomena could result in the 5VSB
voltage drooping excessively and affecting the output
regulation. The solution to a potential problem such as this is
using larger input capacitors with a lower total combined
ESR.
Transistor Selection/Considerations
The HIP6503 usually requires one P-Channel (or bipolar
PNP), two N-Channel MOSFETs and two bipolar NPN
transistors.
One important criteria for selection of transistors for all the
linear regulators/switching elements is package selection for
efficient removal of heat. The power dissipated in a linear
regulator/switching element is
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
Q1
The active element on the 2.5V
MEM
output has to be a
bipolar NPN capable of conducting the maximum active
memory current and exhibit a current gain (h
fe
) of minimum
40 at this current and 0.7V V
CE
.
Q2
The NPN transistor used as sleep state pass element (Q2)
on the 3.3V
DUAL
output has to have a minimum current gain
of 100 at 1.5V V
CE
and 500mA I
CE
throughout the in-circuit
operating temperature range.
Q3, 4, Q2 in 3.3V
MEM
configuration
These N-Channel MOSFETs are used to switch the 3.3V
and 5V inputs provided by the ATX supply into the 3.3V
MEM
,
3.3V
DUAL
/3.3V
SB
, and 5V
DUAL
outputs, while in active (S0,
S1) state. The main criteria for the selection of these
transistors is output voltage budgeting. The maximum
r
DS(ON)
allowed at highest junction temperature can be
expressed with the following equation:
, where
V
INmin
- minimum input voltage
V
OUTmin
- minimum output voltage allowed
I
OUTmax
- maximum output current
The gate bias available for these MOSFETs is of the order of
8V.
Q5
If a P-Channel MOSFET is used to switch the 5VSB output
of the ATX supply into the 5V
DUAL
output during S3 and S5
states (as dictated by EN5VDL status), then the selection
criteria of this device is proper voltage budgeting. The
maximum r
DS(ON)
, however, has to be achieved with only
4.5V of V
GS
, so a logic level MOSFET needs to be selected.
If a PNP device is chosen to perform this function, it has to
have a low saturation voltage while providing the maximum
sleep current and have a current gain sufficiently high to be
saturated using the minimum drive current (typically 20mA).
FIGURE 11. C
OUT4
OUTPUT CAPACITOR
E
)
1
0.1
10
0.01
CAPACITANCE (
μ
F)
10
100
1000
P
LINEAR
I
O
V
IN
V
OUT
–
(
)
×
=
r
DS ON
)
max
V
--------------------------------------------------
V
OUTmax
–
=
HIP6503
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