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參數資料
| 型號： | HIP6503EVAL1 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Multiple Linear Power Controller with ACPI Control Interface |
| 中文描述： | 多重線性電源控制器ACPI控制接口 |
| 文件頁數： | 8/14頁 |
| 文件大小： | 151K |
| 代理商： | HIP6503EVAL1 |
8
Not shown in these diagrams is the deglitching feature used
to protect against false sleep state tripping. Both S3 and S5
pins are protected against noise by a 2
μ
s filter (typically 1 -
4
μ
s). This feature is useful in noisy computer environments if
the control signals have to travel over significant distances.
Additionally, the S3 pin features a 200
μ
s delay in
transitioning to sleep states. Once the S3 pin goes low, an
internal timer is activated. At the end of the 200
μ
s interval, if
the S5 pin is low, the HIP6503 switches into S5 sleep state; if
the S5 pin is high, the HIP6503 goes into S3 sleep state.
Soft-Start Circuit
SOFT-START INTO SLEEP STATES (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence. An
internal 10
μ
A current source charges an external capacitor.
The error amplifiers reference inputs are clamped to a level
proportional to the SS (soft-start) pin voltage. As the SS pin
voltage slews from about 1.25V to 2.5V, the input clamp
allows a rapid and controlled output voltage rise.
Figure 7 shows the soft-start sequence for the typical
application start-up in sleep state with all output voltages
enabled. At time T0 5VSB (bias) is applied to the circuit. At
time T1 the 5VSB surpasses POR level. An internal fast
charge circuit quickly raises the SS capacitor voltage to
approximately 1V, then the 10
μ
A current source continues
the charging. The soft-start capacitor voltage reaches
approximately 1.25V at time T2, at which point the
3.3V
DUAL
/3.3V
SB
and 1.8V
SB
error amplifiers’ reference
inputs start their transition, resulting in the output voltages
ramping up proportionally. The ramp-up continues until time
T3 when the two voltages reach the set value. As the soft-
start capacitor voltage reaches approximately 2.75V, the
under-voltage monitoring circuit of this output is activated
and the soft-start capacitor is quickly discharged to
approximately 1.25V. Following the 3ms (typical) time-out
between T3 and T4, the MSEL and EN5VDL selections are
latched in, and the soft-start capacitor commences a second
ramp-up designed to smoothly bring up the remainder of the
voltages required by the system. At time T5 all voltages are
within regulation limits, and as the SS voltage reaches
2.75V, all the remaining UV monitors are activated and the
SS capacitor is quickly discharged to 1.25V, where it
remains until the next transition. As the 2.5V
CLK
output is
only active while in an active state, it does not come up, but
FIGURE 5. 5V
DUAL
TIMING DIAGRAM FOR EN5VDL = 0;
3V
DUAL
/3V
SB
5VSB
3.3V,
S3
S5
5VDLSB
DLA
3V3DLSB
3V3DL
5VDL
5V, 12V
FIGURE 6. 2.5V
MEM
, 3.3V
MEM
, AND 2.5V
CLK
TIMING DIAGRAM
5VSB
3.3V,
S3
S5
DRV2
VSEN 2
DEVICES
VSEN2
INTERNAL
VCLK
DLA
VSEN1
5V, 12V
FIGURE 7. SOFT-START INTERVAL IN A SLEEP STATE
(ALL OUTPUTS ENABLED)
0V
0V
TIME
SOFT-START
(1V/DIV)
OUTPUT
VOLTAGES
(1V/DIV)
V
OUT1
(1.8V
SB
)
V
OUT3
(3.3V
DUAL
/3.3V
SB
)
V
OUT2
(2.5V
MEM
)
V
OUT5
(5V
DUAL
)
T1 T2
T3
T0
5VSB
(1V/DIV)
T5
T4
V
OUT4
(2.5V
CLK
)
HIP6503
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| HIP6503 | Multiple Linear Power Controller with ACPI Control Interface(集成了多個線性電源控制器的芯片（ACPI控制接口）) |
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| HIP6521CB-T | 功能描述:IC REG QD BCK/LINEAR SYNC 16SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩壓器 - 線性 + 切換式 系列:- 標準包裝:2,500 系列:- 拓撲:降壓（降壓）同步（3），線性（LDO）（2） 功能:任何功能 輸出數:5 頻率 - 開關:300kHz 電壓/電流 - 輸出 1:控制器 電壓/電流 - 輸出 2:控制器 電壓/電流 - 輸出 3:控制器 帶 LED 驅動器:無 帶監控器:無 帶序列發生器:是 電源電壓:5.6 V ~ 24 V 工作溫度:-40°C ~ 85°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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