- 您現在的位置：買賣IC網 > PDF目錄384423 > HIP7010B (HARRIS SEMICONDUCTOR) J1850 Byte Level Interface Circuit PDF資料下載
參數資料
| 型號： | HIP7010B |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 網絡接口 |
| 英文描述： | J1850 Byte Level Interface Circuit |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PDSO14 |
| 文件頁數： | 1/20頁 |
| 文件大小： | 106K |
| 代理商： | HIP7010B |
1
ADVANCE INFORMATION
August 1996
HIP7010
J1850 Byte Level Interface Circuit
Features
Fully Supports VPW (Variable Pulse Width) Messaging
Practices of SAE J1850 Standard for Class B Data
Communications Network Interface
- 3-Wire, High-Speed, Synchronous, Serial Interface
Reduces Wiring Overhead
Directly Interfaces with 68HC05 and 68HC11 Style SPI
Ports
1MHz, 8-Bit Transfers Between Host and HIP7010
Minimize Host Service Requirements
Automatically Transmits Properly Framed Messages
Prepends SOF to First Byte and Appends CRC to Last
Byte
Fail-Safe Design Including, Slow Clock Detection
Circuitry, Prevents J1850 Bus Lockup Due to System
Errors or Loss of Input Clock
Automatic Collision Detection
End of Data (EOD), Break, Idle Bus, and Invalid Symbol
(Noise/Illegal Symbols) Detection
Supports In-Frame Responses with Generation of
Normalization Bits (NB) for Type 1, Type 2, and Type 3
Messages
Wait-For-Idle Mode Reduces Host Overhead During
Non-Applicable Messages
Status Register Flags Provide Information on Current
Status of J1850 Bus
Serial I/O Pins are Active Only During Transfers - Bus
Available for Other Devices 95% of the Time
TEST Pin Provides Built-in-Test Capabilities for
In-System Diagnostics and Factory Testing
High Speed (4X) Receive Mode for Production and
Diagnostic Testing/Programming
Operates with Wide Range of Input Clock Frequencies
Power-Saving Power-Down Mode
Full -40
o
C to +125
o
C Operating Range
Single 3.0V to 6.0V Supply
Description
The Intersil HIP7010, J1850 Byte Level Interface Circuit, is a
member of the Intersil family of low-cost multiplexed wiring
ICs. The integrated functions of the HIP7010 provide the
system designer with components key to building a “Class B”
multiplexed communications network interface, which fully
conforms to the VPW Multiplexed Wiring protocol specified
in the SAE J1850 Standard. The HIP7010 is designed to
interface with a wide variety of Host microcontrollers via a
standard three wire, high-speed (1MHz), synchronous, serial
interface. The HIP7010 automatically produces properly
framed VPW messages,
prepending
the Start of Frame
(SOF) symbol and calculating and appending the CRC
check byte. All circuitry needed to decode incoming mes-
sages, to validate CRC bytes, and to detect Breaks, End of
Data (EOD), Idle bus, and illegal symbols is included. In-
Frame Responses (IFRs) are fully supported for Type 1,
Type 2, and Type 3 messages, with the appropriate Normal-
ization Bit automatically generated. The HCMOS design
allows proper opeSration at various input frequencies from
2MHz to 12MHz. Connection to the J1850 Bus is via a Inter-
sil HIP7020.
Ordering Information
Pinout
HIP7010 (SOIC, PDIP)
TOP VIEW
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
HIP7010P
-40 +125
14 Lead Plastic DIP
E14.3
HIP7010B
-40 +125
14 Lead Plastic SOIC (N)
M14.15
IDLE
VPWIN
VPWOUT
V
DD
RESET
TEST
SACTIVE
RDY
STAT
CLK
V
SS
SIN
SOUT
SCK
1
2
3
4
5
6
7
14
13
12
11
10
9
8
File Number
3644.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
相關PDF資料 |
PDF描述 |
|---|---|
| HIP7010P | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020 | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020AB | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7020AP | FPGA 2000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP7030A0 | J1850 8-Bit 68HC05 Microcontroller Emulator Version |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HIP7010P | 制造商:Rochester Electronics LLC 功能描述:J1850 JBLIC (DIP) - Bulk |
| HIP7010P WAF | 制造商:Harris Corporation 功能描述: |
| HIP7020 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems |
| HIP7020 DIE | 制造商:Harris Corporation 功能描述: |
| HIP7020AB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:J1850 Bus Transceiver For Multiplex Wiring Systems |
發布緊急采購，3分鐘左右您將得到回復。