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參數資料
| 型號： | HM10S604 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 顯示驅動器 |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC |
| 封裝： | TCP |
| 文件頁數： | 5/16頁 |
| 文件大小： | 249K |
| 代理商： | HM10S604 |
CONFIDENT IAL & PROPRIET ARY
HM10S604 PRELIMINARY SPEC
Terminal function
NAME
I/O
DESCRIPTION
DD0 - DD5
DE0 - DE5
DF0 - DF5
I
I
Image signal input terminal
Inputs image signals with a 36-bit width
: 6bit gradation data X 6 dots(for 2 pixels)
Data inputs which select between one of 64 voltages
Dx0 : LSB, Dx5 : MSB
Start pulse I/O
terminal
I/O
Internal shift register’s start pulse
Right shift input
Right shift output
Left shift output
Left shift input
L/R=H
L/R=L
DEIO1
DEIO2
Shift direction selection signal
Right shift (OUT1 ---> OUT420) : H
Left shift (OUT420 ---> OUT1) : L
Shift direction
selection signal
input terminal
I
Shift register clock input terminal
Writes the display data to the data register at the leading edge
Shift clock Input
terminal
I
VDD1 Power supply for digital circuits.
VDD2 Power supply for analog circuits.
P
Potential input terminal for gamma correction
GH63 : The highest voltage in high voltage range.(necessary)
GH0 : The lowest voltage in high voltage range .(necessary)
GL0 : The highest voltage in low voltage range .(necessary)
GL63 : The lowest voltage in low voltage range .(necessary)
GH47/GL47, GH31/GL31, GH15/GL15
: Intermediate D/A voltage references (optional)
Latches the data register contents with leading edge, transfers
it to the D/A converter, and outputs the gradation voltage with
trailing edge.
Gamma correction
reference potential
input terminal
I
I
POLC= L : odd numbered outputs : GH63 ~ GH0
even numbered outputs : GL0 ~ GL63
POLC= H : odd numbered outputs : GL0 ~ GL63
even numbered outputs : GH63 ~ GH0
Polarity control
terminal
I
Selects reversal/non-reversal of input data
RVRS1 : controls reversal/non-reversal of port1.
RVRS2 : controls reversal/non-reversal of port2.
RVRS1,2 = H : reversal
RVRS1,2 = L : non-reversal
This terminal can be processed within TCP. H & L are
identified at the leading edge of each DCLK, like the data.
Input data reverse
terminal
I
TERMINAL
DA0 - DA5
DB0 - DB5
DC0 - DC5
Port1
Image signal input
terminal
Port2
Image signal input
terminal
DEIO1
DEIO2
L/R
DCLK
VDD1
VDD2
GHxx /
GLxx
LOAD
Latch input terminal
POLC
RVRS1
RVRS2
FUNCTION
VSS
Power supply
Ground
G
Ground for digital and analog
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