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參數(shù)資料
| 型號(hào)： | HM62W4100HCLJP-10 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4M High Speed SRAM (1-Mword x 4-bit) |
| 中文描述： | 4分高速SRAM（1 - Mword × 4位） |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 65K |
| 代理商： | HM62W4100HCLJP-10 |
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest
Hitachi’s Sales Dept. regarding specification.
HM62W4100HC Series
4M High Speed SRAM (1-Mword
×
4-bit)
ADE-203-1202 (Z)
Preliminary
Rev. 0.0
Sep. 28, 2000
Description
The HM62W4100HC is a 4-Mbit high speed static RAM organized 1-Mword
×
4-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing
technology. It is most appropriate for the application which requires high speed and high density memory,
such as cache and buffer memory in system. The HM62W4100HC is packaged in 400-mil 32-pin SOJ for
high density surface mounting.
Features
Single supply : 3.3 V
±
0.3 V
Access time : 10 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
All inputs and outputs
Operating current : 115 mA (max)
TTL standby current : 40 mA (max)
CMOS standby current : 5 mA (max)
: 1 mA (max) (L-version)
Data retension current : 0.6 mA (max) (L-version)
Data retension voltage: 2 V (min) (L-version)
Center V
CC
and V
SS
type pinout
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PDF描述 |
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| HM62W4100HCJP-10 | 4M High Speed SRAM (1-Mword x 4-bit) |
| HM62W4100HC | 4M High Speed SRAM (1-Mword x 4-bit) |
| HM62W4100HJP-12 | 4M High Speed SRAM (1-Mword x 4-bit) |
| HM62W4100HJP-15 | 4M High Speed SRAM (1-Mword x 4-bit) |
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