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參數(shù)資料
型號(hào): HMC463
廠商: 美國(guó)訊泰微波有限公司上海代表處
元件分類: FPGA
英文描述: 800000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述: GaAs PHEMT MMIC低噪聲放大器,直流- 20.0千兆赫
文件頁(yè)數(shù): 1/8頁(yè)
文件大小: 279K
代理商: HMC463
MICROWAVE CORPORATION
1 - 98
For price, delivery, and to place orders, please contact Hittite Microwave Corporation:
12 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373
Order Online at www.hittite.com
A
1
HMC463
GaAs PHEMT MMIC LOW NOISE
AGC AMPLIFIER, 2.0 - 20.0 GHz
v03.0304
General Description
Features
Gain: 14 dB
Functional Diagram
The HMC463 is a GaAs MMIC PHEMT Low Noise
AGC Distributed Amplifier die which operates
between 2 and 20 GHz. The amplifier provides 14
dB of gain, 2.5 dB noise figure and 19 dBm of output
power at 1 dB gain compression while requiring only
60 mA from a +5V supply. An optional gate bias
(Vgg2) is provided to allow Adjustable Gain Control
(AGC) of 10 dB typical. Gain flatness is excellent
at ±0.15 dB from 6 - 18 GHz making the HMC463
ideal for EW, ECM and RADAR applications. The
HMC463 amplifier can easily be integrated into
Multi-Chip-Modules (MCMs) due to its small size.
All data is with the chip in a 50 Ohm test fixture con-
nected via 0.025mm (1 mil) diameter wire bonds of
minimal length 0.31mm (12 mils).
Noise Figure: 2.5 dB @ 10 GHz
P1dB Output Power: +19 dBm @ 10 GHz
Supply Voltage: +5.0V @ 60 mA
50 Ohm Matched Input/Output
3.15 mm x 1.63 mm x 0.1 mm
Typical Applications
The HMC463 is ideal for:
Telecom Infrastructure
Microwave Radio & VSAT
Military & Space
Test Instrumentation
Fiber Optics
Electrical Specifications,
T
A
= +25° C, Vdd= 5V, Idd= 60 mA*
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
Frequency Range
2.0 - 6.0
6.0 - 18.0
18.0 - 20.0
GHz
Gain
12
15
12
14
12
14
dB
Gain Flatness
±1.0
±0.15
±0.15
dB
Gain Variation Over Temperature
0.015
0.025
0.015
0.025
0.015
0.025
dB/ °C
Noise Figure
3.0
4.0
2.5
3.7
3.5
4.0
dB
Input Return Loss
12
15
14
dB
Output Return Loss
11
12
10
dB
Output Power for 1 dB Compression (P1dB)
16
19
13
16
11
14
dBm
Saturated Output Power (Psat)
21
20
19
dBm
Output Third Order Intercept (IP3)
31
28
26
dBm
Supply Current
(Idd) (Vdd= 5V, Vgg1= -0.9V Typ.)
60
60
60
mA
* Adjust Vgg1 between -1.5 to -0.5V to achieve Idd= 60 mA typical.
Vgg2: Optional Gate Bias for AGC
相關(guān)PDF資料
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HMC463LP5 800000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
HMC464 800000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
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HMC465 800000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
HMC465LP5 800000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
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