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參數資料
| 型號： | HMP8117 |
| 廠商： | Intersil Corporation |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | NTSC / PAL視頻解碼器 |
| 文件頁數： | 25/45頁 |
| 文件大小： | 269K |
| 代理商： | HMP8117 |
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25
TABLE 15. GENLOCK CONTROL REGISTER
SUB ADDRESS = 04
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
Aspect Ratio
Mode
0 = Rectangular (BT.601) pixels
1 = Square pixels
0
B
6
Freeze Output
Timing Enable
Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit to a “0”
resumes normal operation at the start of the next field.
0 = Normal operation
1 = Freeze output timing
0
B
5
DVALID Duty Cycle
Control
(DVLD_DCYC)
This bit is ignored during the 8-bit YCbCr and BT.656 output modes.
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID has 50/50 duty cycle at the pixel output data rate
1 = DVALID goes active based on line-lock. This will cause DVALID to not have a 50/50 duty
cycle. This bit is intended to be used in maintaining backward compatibility with the HMP8112A
DVALID output timing.
0
B
4
DVALID Line Timing
Control
(DVLD_LTC)
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID present only during active video time on active scan lines
1 = DVALID present the entire scan line time on all scan lines
During the 8-bit YCbCr and BT.656 output modes, this bit defines the DVALID output as:
0 = Normal timing
1 = DVALID signal ANDed with CLK2
0
B
3
Missing HSYNC
Detect Select
This bit specifies the number of missing horizontal sync pulses before entering horizontal lock
acquisition mode.
0 = 12 pulses
1 = 1 pulse
1
B
2
Missing VSYNC
Detect Select
This bit specifies the number of missing vertical sync pulses before entering vertical lock
acquisition mode.
0 = 3 pulses
1 = 1 pulse
0
B
1-0
CLK2 Frequency
This bit indicates the frequency of the CLK2 input clock.
00 = 24.54MHz10 = 29.5MHz
01 = 27.0MHz11 = Reserved
01
B
TABLE 16. ANALOG INPUT CONTROL REGISTER
SUB ADDRESS = 05
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-6
Lock Loss
Video Gain
Select
If bits 5-4 do not equal “01”, these bits indicate what mode the AGC circuitry will be after loss of
sync. If bits 5-4 equal “01”, these bits are ignored.
00 = Automatic gain control: bits 5-4 will be reset to “01”
01 = Maintain fixed gain: bits 5-4 will not be changed
10 = Normal AGC switching to fixed gain after lock achieved: bits 5-4 will not be reset to “01”
unless they indicated “freeze automatic gain control”
11 = reserved
00
B
5-4
Video Gain
Control Select
00 = Fixed 1x gain
01 = Automatic gain control
10 = Fixed gain control. (Use gain factor from Video Gain Adjust register 1D
H
.)
11 = Freeze automatic gain control
01
B
3
Digital Anti-Alias
Filter Control
0 = Internal digital anti-alias filter is active.
1 = Internal digital anti- alias filter is bypassed. (Not Recommended)
0
B
2-0
Video Signal
Input Select
000 = CVBS1
001 = CVBS2
010 = CVBS3
011 = S-video
1XX = reserved
000
B
HMP8117
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PDF描述 |
|---|---|
| HMP8117CN | NTSC/PAL Video Decoder |
| HMP8154 | NTSC/PAL Encoders |
| HMP8154CN | NTSC/PAL Encoders |
| HMP8156A | NTSC/PAL Encoders |
| HMP8154EVAL1 | NTSC/PAL Encoders |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HMP8117_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Video Decoder |
| HMP8117CN | 功能描述:編碼器、解碼器、復用器和解復用器 80PQFP,0+70C NTSC/PAL VIDEO DECODER W/MA RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HMP8117CN96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8117CNZ | 功能描述:編碼器、解碼器、復用器和解復用器 W/ANNEAL 80PQFP 0+70 DECODER W/MA RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HMP8154 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
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