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參數資料
| 型號： | HMP8117CN |
| 廠商： | INTERSIL CORP |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | NTSC/PAL Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PDSO80 |
| 封裝： | PLASTIC, MS-022GB-1, MQFP-80 |
| 文件頁數： | 36/45頁 |
| 文件大小： | 269K |
| 代理商： | HMP8117CN |
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36
TABLE 58. END V_BLANK REGISTER
SUB ADDRESS = 35
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate BLANK
Output Signal
This 8-bit register specifies the line number to negate BLANK each field.
For NTSC operation, it occurs on line (n + 5) on odd fields and line (n + 268) on even fields. For
PAL operation, it occurs on line (n + 5) on odd fields and line (n + 318) on even fields.
12
H
TABLE 59. END HSYNC REGISTER
SUB ADDRESS = 36
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Negate HSYNC
Output Signal
This 8-bit register specifies the horizontal count at which to negate HSYNC each scan line.
Values may range from 0 (0000 0000) to 510 (1111 1111) CLK2 cycles. The leading edge of
HSYNC is count 00
H
.
30
H
TABLE 60. HSYNC DETECT WINDOW REGISTER
SUB ADDRESS = 37
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Horizontal Sync
Detect Window
This 8-bit register specifies the width of the timing window (in 1x clock samples) for the digital
PLL to accept horizontal sync pulses in each line. The window is centered about where the
horizontal sync pulse should be located.
If the horizontal sync pulse falls inside the window, the digital PLL maintains normal lock timing.
If the horizontal sync pulse falls outside this window, the digital PLL will to enter the horizontal
lock acquisition mode based on the current setting for bits 3-2 of register 04
H
. Recommend
changing this register to 90
H
following reset in order to widen the window for poorly timed input
video sources.
20
H
(Use 90
H
)
TABLE 61. MV CONTROL
SUB ADDRESS = 41
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7
MV Stripe Detection
and Bypass Enable
Set to “1” to enable the detection and bypass of the MV Color Striping component. If this bit is
not enabled and the MV Color Striping component exists on the input signal, artifacts will be
clearly visible as horizontal streaks in the output data. This bit must be enabled for the MV
Detection Status of register 0E
H
to be updated.
0
B
6
MV PSP Detection
Enable
Set to “1” to enable detection of the MV Pseudo Sync Pulse (PSP)
component. If the MV PSP component exists on the input signal, this bit must be enabled for the
MV Detection Status of register 0E
H
to be updated.
0
B
5-3
MV PSP Detection
Count
Defines the number of extra sync pulses required before declaring the Pseudo Sync Pulse (PSP)
component in the MV Detection Status of register 0E
H
. The PSP component must also be
present for the number of fields defined in bits 2-0 below.
100
B
2-0
MV Detection
Field Count
Defines the minimum number of fields that an MV component must be present for in order to
change the MV Detection Status of register 0E
H
. Add 2 to bits 2-0 to obtain the minimum field
count. Ex: The default of 110
B
is actually 6 + 2 = 8 fields.
110
B
TABLE 62. RESERVED
SUB ADDRESS = 42
H
BIT
NO.
FUNCTION
DESCRIPTION
RESET
STATE
7-0
Reserved
Set bits 5-4 to 11
B
for optimum performance.
00
H
(Use 30
H
)
HMP8117
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相關代理商/技術參數 |
參數描述 |
|---|---|
| HMP8117CN96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HMP8117CNZ | 功能描述:編碼器、解碼器、復用器和解復用器 W/ANNEAL 80PQFP 0+70 DECODER W/MA RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| HMP8154 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8154_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:NTSC/PAL Encoders |
| HMP8154CN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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