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參數資料
| 型號： | HMS81020TL |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | Hynix半導體公司的8位單芯片微控制器 |
| 文件頁數： | 49/77頁 |
| 文件大小： | 1112K |
| 代理商： | HMS81020TL |
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HMS81004E/08E/16E/24E/32E
46
JUNE 2001 Ver 1.00
3) Single/Modulo-N Mode
Timer0 (Timer1) can select initial (T0INIT, T1INIT of
TM01) output level of Timer Output port. If initial level is
“L”, Low-Data Register value of Timer Data Register is
transferred to comparator and T0OUT (T1OUT) is to be
“Low”, if initial level is High High -Data Register is
transferred and to be “High”. Single Mode can be set by
Mode Select bit (T0MOD, T1MOD) of Timer Mode Reg-
ister (TM0, TM1) to “1” When used as Single Mode, Tim-
er counts up and compares with value of Data Register. If
the result is same, Time Out interrupt occurs and level
of Timer Output port toggle, then counter stops as reset
state. When used as Modulo-N Mode, T0MOD (T1MOD)
should be set “0”. Counter counts up until the value of
Data Register and occurs Time-out interrupt. The level of
Timer Output port toggle and repeats process of
counting the value which is selected in Data Register.
During Modulo-N Mode, If interrupt select bit (T0IFS,
T1IFS) of Mode Register is “0”, Interrupt occurs on every
Time-out. If it is “1”, Interrupt occurs every second time-
out.
Note:
Timer Output is toggled whenever time out happen
(4) Timer 2
Timer2 operates as a up-counter. The content of T2DR are
compared with the contents of up-counter. If a match is
found. Timer2 interrupt (IFT2) is generated and the up-
counter is cleared to “00h”. Therefore, Timer2 executes
as a interval timer. Interrupt period is determined by the
count source clock for the Timer2 and content of T2DR.
When T2ST is set to “1”, count value of Timer 2 is cleared
and starts counting-up. For clearing and starting the
Timer2. T2ST have to set to “1” after set to “0”. In order to
write a value directly into the T2DR, T2ST should be set
to “0”. Count value of Timer2 can be read at any time.
Figure 13-8 Operation Diagram for Single/Modulo-N Mode
[ Single Mode ]
[ Module-N Mode ]
8bit/16bit
counting
Timer Enable initial
value toggle
8bit/16bit
counting
Timer Enable initial
value toggle
Timer-output toggle
Int occurs (IFS=1) Each 2nd time out
Int occurs (IFS=0) when Time out
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