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參數(shù)資料
| 型號： | HMS87C1302AD |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | SOP-24 |
| 文件頁數(shù)： | 57/70頁 |
| 文件大小： | 977K |
| 代理商： | HMS87C1302AD |
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HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
Jan. 2001
Preliminary
57
of the STOP feature. This point should be little current
flows when the input level is stable at the power voltage
level (V
DD
/V
SS
), however, when the input level gets high-
er than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal into the
high-impedance state, a current flow across the ports input
transistor, requiring to fix the level by pull-up or other
means.
Release the STOP mode
The exit from STOP mode is hardware reset or external in-
terrupt. Reset re-defines all the Control registers but does
not change the on-chip RAM. External interrupts allow
both on-chip RAM and Control registers to retain their val-
ues.
After releasing STOP mode, instruction execution is divid-
ed into two ways by I-flag(bit2 of PSW).
If I-flag = 1, the normal interrupt response takes place. If I-
flag = 0, the chip will resume execution starting with the
instruction following the STOP instruction. It will not vec-
tor to interrupt service routine. (refer to )
When exit from Stop mode by external interrupt, enough
oscillation stabilization time is required to normal opera-
tion. shows the timing diagram. When release the Stop
mode, the Basic interval timer is activated on wake-up. It
is increased from 00
H
until FF
H
. The count overflow is set
to start normal operation. Therefore, before STOP instruc-
tion, user must be set its relevant prescaler divide ratio to
have long enough time (more than 20msec). This guaran-
tees that oscillator has started and stabilized.
By reset, exit from Stop mode is shown in .
Minimizing Current Consumption in Stop Mode
The Stop mode is designed to reduce power consumption.
To minimize the current consumption during Stop mode,
the user should turn-off output drivers that are sourcing or
sinking current, if it is practical. Weak pull-ups on port
pins should be turned off, if possible. All inputs should be
either as V
SS
or at V
DD
(or as close to rail as possible).
An intermediate voltage on an input pin causes the input
buffer to draw a significant amount of current.
Figure 17-1 STOP Releasing Flow by Interrupts
Figure 17-2 Timing of STOP Mode Release by External Interrupt
IEXX
=0
=1
STOP
INSTRUCTION
STOP Mode
Interrupt Request
STOP Mode Release
I-FLAG
=1
Interrupt Service Routine
Next
INSTRUCTION
=0
Master Interrupt
Enable Bit PSW[2]
Corresponding Interrupt
Enable Bit (IENH, IENL)
~
STOP Mode
Normal Operation
Oscillator
(X
IN
pin)
~
~
N+1
N
N+2
00
01
FE
FF
00
01
N-1
N-2
~
~
~
~
~
Clear Basic Interval Timer
STOP Instruction Execution
Normal Operation
Stabilization Time
t
ST
> 20mS
Internal
Clock
External
Interrupt
BIT
Counter
~
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