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參數資料
| 型號： | HMS87C1302AD |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | SOP-24 |
| 文件頁數： | 62/70頁 |
| 文件大?。?/td> | 977K |
| 代理商： | HMS87C1302AD |
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HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
62
Preliminary
Jan. 2001
19. POWER FAIL PROCESSOR
The HMS87C1304A and HMS87C1302A has an on-chip
power fail detection circuitry to immunize against power
noise. A configuration register, PFDR, can enable (if clear/
programmed) or disable (if set) the Power-fail Detect cir-
cuitry. If V
DD
falls below 2.5~3.5V(2.0~3.0V) range for
longer than 50 nS, the Power fail situation may reset MCU
according to PFS bit of PFDR. And power fail detect level
is selectable by mask option. On the other hand, in the
OTP, power fail detect level is decided by setting the bit
PFDLEVEL of CONFIG register when program the OTP.
As below PFDR register is not implemented on the in-cir-
cuit emulator, user can not experiment with it. Therefore,
after final development of user program, this function may
be experimented.
Note:
Power fail detect level is decided by mask option
checking the bit PFDLEVEL of MASK ORDER
SHEET (refer to MASK ORDER SHEET)
In thc case of OTP, Power fail detect level is decid-
ed by setting the bit PFDLEVEL of CONFIG register
(refer to Figure 20-1 .
Figure 19-1 Power Fail Detector Register
Figure 19-2 Example S/W of RESET by Power fail
PFDR
ADDRESS : EFH
RESET VALUE : -----100
-
-
-
-
-
PFDIS
PFDM
PFS
Reserved
Power Fail Status
0 : Normal Operate
1 : This bit force to “1” when
Power fail was detected
Operation Mode
0 : System Clock Freeze during power fail
1 : MCU will be reset during power fail
Disable Flag
0 : Power fail detection enable
1 : Power fail detection disable
Power Fail Detector Register
FUNTION
EXECUTION
INITIALIZE RAM DATA
PFS =1
NO
RESET VECTOR
INITIALIZE ALL PORTS
INITIALIZE REGISTERS
RAM CLEAR
YES
Skip the
initial routine
Preimnary
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