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參數資料
| 型號： | HS0-54C138RH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer |
| 中文描述： | CMOS SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, UUC16 |
| 封裝： | DIE-16 |
| 文件頁數： | 2/4頁 |
| 文件大?。?/td> | 536K |
| 代理商： | HS0-54C138RH-Q |
2
Typical Applications
Typical applications include systems which require multiple
input/output ports and memories. When the HS-54C138RH
is enabled one of the eight outputs will go low. This output
can be used to select a particular device or a group of
devices. The HS-54C138RH can also be cascaded to
provide an enabling scheme for larger systems and allow
one decoder to control eight other decoders as in Figure 1.
Figure 2 shows a configuration that can be used to enable
multiple I/O ports or memory devices. Up to 24 memory
devices or I/O ports can be controlled using this circuit.
For demultiplexer operation, one of the three enable inputs
is used as the data input while the other two inputs are
enable. The transmitted data is distributed to the proper
output as determined by the 3-line select inputs. See Figure
3.
FIGURE 1.
FIGURE 2.
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
SELECT A
ENABLE
HS-54C138RH
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
HS-54C138RH
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
HS-54C138RH
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
HS-54C138RH
“0”
“1”
“0”
“1”
“0”
“1”
TO OTHER
DEVICES
SELECT B
ENABLE
ENABLE
ENABLE
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
G1 G2B G2A
C
B
A
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
G1 G2B G2A
C
B
A
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
G1 G2B G2A
C
B
A
EN
EN
EN A4
A3
A2 A1 A0
PORT NUMBERS OR CHIP SELECTS
HS-54C138RH
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| HS1-54C138RH-8 | Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer |
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