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參數資料
| 型號： | HT27C040 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 512K x 8-Bit CMOS OTP EPROM(512K x 8位 CMOS一次可編程EPROM) |
| 中文描述： | 為512k × 8位檢察官辦公室的CMOS存儲器（為512k × 8位的CMOS一次可編程存儲器） |
| 文件頁數： | 7/10頁 |
| 文件大小： | 110K |
| 代理商： | HT27C040 |
Preliminary
HT27C040
7
August 29, 2000
to output (t
CE
). Data is available at the outputs
(t
OE
) after the falling edge of OE, assuming the
CE has been LOW and addresses have been
stable for at least t
ACC
-t
OE
.
Standby mode
The HT27C040 has CMOS standby mode which
reduces the maximum VCC current to 10 A. It
is placed in CMOS standby when CE is at
V
CC
0.3V. The HT27C040 also has a
TTL-standby mode which reduces the maxi-
mum VCC current to 1.0mA. It is placed in
TTL-standby when CE is at V
IH
. When in
standby mode, the outputs are in a
high-impedance state, independent of the OE
input.
Two-line output control function
Toaccommodatemultiplememoryconnections,a
two-linecontrolfunctionisprovidedtoallowfor:
Low memory power dissipation
Assurance that output bus contention will not
occur
ItisrecommendedthatCEbedecodedandused
as the primary device-selection function, while
OE be made a common connection to the READ
line from the system control bus. This assures
that all deselected memory devices are in their
low-power standby mode and that the output
pins are only active when data is desired from a
particular memory device.
System considerations
During the switch between active and standby
conditions, transient current peaks are pro-
duced on the rising and falling edges of Chip
Enable. The magnitude of these transient cur-
rent peaks is dependent on the output capaci-
tance loading of the device. At a minimum, a
0.1 Fceramiccapacitor(highfrequency,lowin-
herent inductance) should be used on each de-
vice between VCC and VPP to minimize
transient effects. In addition, to overcome the
voltage drop caused by the inductive effects of
the printed circuit board traces on EPROM ar-
rays, a 4.7 F bulk electrolytic capacitor should
be used between VCC and VPP for each eight
devices. The location of the capacitor should be
close to where the power supply is connected to
the array.
Operation mode truth table
All the operation modes are shown in the table following.
Mode
CE
OE
A0
A1
A9
VPP
Output
Read
V
IL
V
IL
V
IH
V
IL
V
IH
X
X
X
X
V
CC
V
CC
V
CC
V
CC
Dout
Output Disable
X
X
X
High Z
Standby (TTL)
X
X
X
High Z
Standby (CMOS)
V
CC
0.3V
V
IL
X
X
X
X
X
High Z
Program
V
IH
V
IL
X
X
X
X
V
PP
V
PP
V
PP
V
CC
V
CC
D
IN
D
OUT
High Z
Program Verify
X
X
X
Product Inhibit
V
IH
V
IL
V
IL
X
X
X
Manufacturer Code (3)
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
H
(1)
V
H
(1)
1C
Device Type Code (3)
04
Note: (1) V
H
= 12.0V
0.5V
(2) X=Either V
IH
or V
IL
(3)ForManufacturerCodeandDeviceCode,A1=V
IH
,WhenA1=V
IL
,bothcodeswillread7F
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