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參數資料
| 型號： | HT48R50A |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 數學處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 16/46頁 |
| 文件大小： | 1037K |
| 代理商： | HT48R50A |
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HT48R50A-1
Rev. 1.10
16
July 2, 2001
tion, only one can be active depending on the
ROM code option
"CLR WDT times selection
option". If the "CLR WDT" is selected (i.e.
CLRWDT times equal one), any execution of
the "CLR WDT" instruction will clear the WDT.
In the case that "CLR WDT1" and "CLR WDT2"
are chosen (i.e. CLRWDT times equal two),
these two instructions must be executed to
clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
Power down operation
HALT
The HALT mode is initialized by the "HALT"
instruction and results in the following...
The system oscillator will be turned off but
the WDT oscillator remains running (if the
WDT oscillator is selected).
The contents of the on chip RAM and regis-
ters remain unchanged.
WDT and WDT prescaler will be cleared and
recounted again (if the WDT clock is from the
WDT oscillator).
All of the I/O ports maintain their original sta-
tus.
The PD flag is set and the TO flag is cleared.
ThesystemcanleavetheHALTmodebymeans
of an external reset, an interrupt, an external
falling edge signal on port A or a WDT overflow.
An external reset causes a device initialization
and the WDT overflow performs a "warm re-
set". After the TO and PD flags are examined,
the reason for chip reset can be determined.
The PD flag is cleared by system power-up or
executingthe"CLRWDT"instructionandisset
when executing the "HALT" instruction. The
TO flag is set if the WDT time-out occurs, and
causes a wake-up that only resets the PC and
SP; the others remain in their original status.
The port A wake-up and interrupt methods can
be considered as a continuation of normal exe-
cution. Each bit in port A can be independently
selected to wake up the device by mask option.
Awakening from an I/O port stimulus, the pro-
gram will resume execution of the next instruc-
tion. If it awakens from an interrupt, two
sequence may occur. If the related interrupt is
disabled or the interrupt is enabled but the
stack is full, the program will resume execution
at the next instruction. If the interrupt is en-
abledandthestackisnotfull,theregularinter-
rupt response takes place. If an interrupt
request flag is set to "1" before entering the
HALT mode, the wake-up function of the re-
lated interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
SYS
(sys-
tem clock period) to resume normal operation.
Inotherwords,adummyperiodwillbeinserted
after a wake-up. If the wake-up results from an
interrupt acknowledge signal, the actual inter-
rupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the
nextinstructionexecution,thiswillbeexecuted
immediately after the dummy period is fin-
ished.
To minimize power consumption, all the I/O
pins should be carefully managed before enter-
ing the HALT status. The RTC oscillator still
runs in the HALT mode (if the RTC oscillator is
enabled).
Reset
Therearethreewaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a "warm reset" that resets only the PC
and SP, leaving the other circuits in their origi-
nal state. Some registers remain unchanged
during other reset conditions. Most registers
are reset to the initial condition when the re-
set conditions are met. By examining the PD
and TO flags, the program can distinguish be-
tween different "chip resets".
TO PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal
operation
1
1
WDT wake-up HALT
Note: "u" stands for "unchanged"
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相關代理商/技術參數 |
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| HT48R50A-1 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit MCU |
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