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參數資料
| 型號： | HT6116-70 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | CMOS 2K??8-Bit SRAM |
| 中文描述： | 的CMOS 2K？？8位SRAM |
| 文件頁數： | 5/10頁 |
| 文件大小： | 305K |
| 代理商： | HT6116-70 |
Timing Diagrams
Read cycle
(1)
Functional Description
The HT6116-70 is a 2K
×
8 bit SRAM. When the
CS pin of the chip is set to “low”, data can be
written in or read from eight data pins; other-
wise, the chip is in the standby mode. During a
write cycle, the data pins are defined as the
input state by setting the WE pin to low. Data
should be ready before the rising edge of the WE
pin according to the timing of the writing cycle.
While in the read cycle, the WE pin is set to high
and the OE pin is set to low to define the data
pins as the output state. All data pins are de-
fined as a three-state type, controlled by the OE
pin. In both cycles (namely, write and read cy-
cles), the locations are defined by the address
pins A0~A10. The following table illustrates the
relations of WE , OE , CS and their correspond-
ing mode.
CS
OE
WE
Mode
D0~D7
H
X
X
Standby
High–Z
L
L
H
Read
Dout
L
H
H
Read
High–Z
L
X
L
Write
Din
where
X stands for “don’t care”.
H stands for high level
L stands for low level.
HT6116-70
5
3rd J uly ’97
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