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參數(shù)資料
| 型號： | HT82J30R |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 16 Channel A/D MCU with SPI Interface |
| 中文描述： | 16通道A / D轉(zhuǎn)換，SPI接口單片機 |
| 文件頁數(shù)： | 10/47頁 |
| 文件大小： | 312K |
| 代理商： | HT82J30R |
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HT82J30R/HT82J30A
Rev. 1.00
10
December 20, 2006
counter interrupt request flag is set, a subroutine call to
location 00CH will occur. The related interrupt request
flag will be reset and the EMI bit cleared to disable fur-
ther interrupts.
The A/D converter end-of-conversion interrupt is initial-
ized by setting the A/D end-of-conversion interrupt re-
quest flag (bit 6 of INTC), caused by an end of A/D
conversion. When the interrupt is enabled, the stack is
not full and the end of A/D conversion interrupt request
flag is set, a subroutine call to location 0CH will occur.
The related interrupt request flag will be reset and the
EMI bit cleared to disable further interrupts.
There are two serial interface interrupts, which will be
generated when the interface receives or transmits
8-bits of data. These interrupts are indicated by the in-
terrupt flags, SIF_A; bit 4 of INTC1, and SIF_B; bit 5 of
INTC1. The serial interface interrupts are enabled by
setting the serial interface interrupt control bits, ESII_A;
bit 0 of INTC1 and ESII_B; bit 1 of INTC1. After the re-
spective interface is enabled by setting the
corresponding SBEN bit, which is bit 4 of either
SBCR_A or SBCR_B, if the stack is not full and the
corresponding SIF_A or SIF_B bit is set, a subroutine
call to location 10H or 14H occurs.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bits are set to 1 (if the stack is not full).
To return from the interrupt subroutine, a
RET
or
RETI instruction may be executed. RETI will set the
EMI bit to enable further interrupts, but RET will not.
Interrupts, occurring in the interval between rising edge
of two consecutive T2 pulses, will be serviced on the
later of the two T2 pulses, if the corresponding interrupts
are enabled. In the case of simultaneous requests the
priorities in the follow table apply.
These can be masked by clearing the EMI bit.
Interrupt Source
Priority
Vector
INT0 External Interrupt
1
04H
Timer/Event Counter Overflow
2
08H
EndofA/DConversionInterrupt
3
0CH
SPI_A Interrupt
4
10H
SPI_B Interrupt
5
14H
INT1 External Interrupt
6
18H
The timer/event counter interrupt request flag (TF), exter-
nalinterruptrequestflag(EIF),A/Dconverterrequestflag
(ADF),enabletimer/eventcounterbit(ETI),enableexter-
nal interrupt bit (EEI), enable A/D converter interrupt bit
(EADI) and enable master interrupt bit (EMI) constitute
an interrupt control register (INTC) which is located at
0BHinthedatamemory.EMI,EEI,ETI,EADIareusedto
control the enabling/disabling of interrupts. These bits
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI_A
Controls the external interrupt (1= enabled; 0= disabled)
2
ETI
Controls the Timer/Event Counter interrupt (1= enabled; 0= disabled)
3
EADI
Controls the A/D converter interrupt (1= enabled; 0= disabled)
4
EIF_A
External interrupt request flag (1= active; 0= inactive)
5
TF
Internal Timer/Event Counter request flag (1= active; 0= inactive)
6
ADF
End of A/D conversion interrupt request flag (1= active; 0= inactive)
7
Unused bit, read as 0
INTC (0BH) Register
Bit No.
Label
Function
0
ESII_A
Controls the serial interface interrupt (1= enabled; 0= disabled)
1
ESII_B
Controls the serial interface interrupt (1= enabled; 0= disabled)
2
EEI_B
Controls the INT1 external interrupt (1= enabled; 0= disabled)
3, 7
Unused bits, read as 0
4
SIF_A
Serial interface interrupt request flag (1= active; 0= inactive)
5
SIF_B
Serial interface interrupt request flag (1= active; 0= inactive)
6
EIF_B
INT1 External interrupt request flag (1= active; 0= inactive)
INTC1 (1EH) Register
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