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參數資料
| 型號： | HT82M9BEE |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | USB Mouse Encoder 8-Bit MCU with EEPROM |
| 中文描述： | USB鼠標編碼器8位微控制器帶有EEPROM |
| 文件頁數： | 9/47頁 |
| 文件大小： | 336K |
| 代理商： | HT82M9BEE |
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HT82M9BEE/HT82M9BAE
Rev. 1.20
9
August 13, 2007
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and Logic Unit
ALU
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register
STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, opera-
tions related to the status register may give different re-
sults from those intended.
The TO flag can be affected only by a system power-up,
a WDT time-out or executing the CLR WDT or HALT
instruction. The PDF flag can be affected only by exe-
cuting the HALT or CLR WDT instruction or during a
system power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, upon entering the interrupt sequence or exe-
cuting a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
tosettheenable/disableandtheinterruptrequestflags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the inter-
rupt request will not be acknowledged, even if the re-
lated interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be pre-
vented from becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
1 1 =
1
=
1
=
1 + =
1 . =
1 3 =
1 4 =
1 5 =
1 7 =
1 6 =
1
=
1 & =
1
=
1
=
1
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1 8 =
1 =
=
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+ =
. =
3 =
4 =
5 =
7 =
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& =
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8 =
1 =
!
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1
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&
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& "
& " =
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1
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C
8 8
1
8 8
8 8
8 8
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6 =
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. 3 =
. 4 =
. 5 =
. 7 =
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Bank 1 RAM Mapping
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