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參數資料
| 型號： | HT82V24 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 16-Bit, 15MSPS, 3-Channel CCD/CIS Analog Signal Processor |
| 中文描述： | 16位，15MSPS，3通道防治荒漠化公約/獨聯體模擬信號處理器 |
| 文件頁數： | 13/21頁 |
| 文件大小： | 216K |
| 代理商： | HT82V24 |
Application Circuits
The recommended circuit configuration for the 3-channel CDS mode operation is shown in the figure below (ADI mode
data output format). The recommended input coupling capacitor value is 0.1 F.
Asingle ground plane is recommended for the HT82V24. Aseparate power supply may be used for DRVDD, the digital
driver supply, but this supply pin should still be decoupled to the same ground plane as with the rest of the HT82V24.
Theloadingofthedigitaloutputsshouldbeminimized,eitherbyusingshorttracestothedigitalASIC,orbyusingexter-
nal digital buffers. To minimize the effect of digital transients during major output code transitions, the falling edge of the
CDSCLK2 should occur in coincidence with or before the rising edge of ADCCLK. All 0.1 F decoupling capacitors
should be located as close as possible to the HT82V24 pins. When operating in a single channel mode, the unused an-
alog inputs should be grounded.
Note:
For the 3-channel SHA mode, all of the above considerations also apply for this configuration, except that the
analog input signals are directly connected to the HT82V24 without the use of coupling capacitors. The OFF-
SETpin should be grounded if the inputs to the HT82V24 are to be referenced to ground, or a DC offset voltage
should be applied to the OFFSET pin in the case where a coarse offset needs to be removed from the inputs.
The analog input signals must already be dc-biased between 0V and 2V, if OFFSET is connected to ground.
HT82V24
Rev. 1.00
13
September 7, 2005
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