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參數資料
| 型號： | HWB1151 |
| 廠商： | Intersil Corporation |
| 英文描述： | () |
| 中文描述： | （） |
| 文件頁數： | 5/13頁 |
| 文件大?。?/td> | 135K |
| 代理商： | HWB1151 |
5
Functional Overview
The Radio Card is based on the Intersil PRISM Direct
Sequence Chip Set.
There are ten basic units in this card:
1. Baseband Processor
2. Modulator/Demodulator
3. Dual Synthesizer
4. Up/Down Converter
5. Power Amplifier
During transmission, the data to be transmitted should be
placed on the TX data line going into the baseband
processor. This data will be modulated according to the
format selected (CCK, MBOK, DBPSK or DQPSK) and then
spread using a programmable PN code. Two signals will be
generated (I & Q).
6. Low Noise Amplifier (LNA)
7. RF VCO
8. IF VCO
9. Antenna
10. Buffer Interface
The I & Q signals are sent to the Modulator/Demodulator
where they will be first filtered and then modulated with the
IF frequency (280MHz). The IF oscillator generates 560MHz
which is divided by two inside the Modulator/Demodulator,
so the final IF signal is 280MHz. Next, the two signals are
combined into a single signal and sent over to the Up/Down
converter.
The Up/Down converter will shift this signal to the RF
channel programmed in the synthesizer, in the 2.4GHz ISM
band.
In the final stage this signal is amplified to produce a typical
power output of 18dBm, measured in the middle of the ISM
Band at the antenna.
In the receive mode, the radio signal is received by one of
the two external antennas. The antenna selected is option-
ally determined by an Antenna Diversity algorithm in the
Baseband Processor which compares the quality of the
received signal in each antenna during the Preamble and
selects the better signal. This substantially improves the
multipath performance of the assembly. Alternately, the
antenna selection may be directly controlled by the software.
The signal is amplified by the LNA, and then sent to the
Up/Down converter. The Up/Down converter down-converts
this signal from the 2.4GHz range to the IF frequency,
280MHz.
The Modulator/Demodulator converts the signal to
baseband and splits the signal into the In-Phase (I) and
Quadrature (Q) components, before it is sent to the
Baseband Processor.
Finally, the Baseband Processor despreads and
demodulates the data from DBPSK or DQPSK form, and
places it on the RX data line.
The bidirectional Buffer Translators are used to interface
between computer 5V and card 3.5V logic.
The RF and IF Local Oscillator signals are generated using
the synthesizer and the voltage controlled oscillators. The
dual synthesizer should be programmed with the desired RF
channel frequency less the IF frequency.
Example:
RF
IF
CH1
2412MHz - 280MHz = 2132MHz
The baseband processor and the synthesizer are driven
from a common 44MHz oscillator to control the timing of
these chips.
Refer to Application Note AN9624 [1] for a more detailed
radio description.
Edge Connector Pin Descriptions
The block diagram in Figure 1 shows control signal
connections from the edge connector to the radio integrated
circuits.
LO
FIGURE 1. CONTROL SIGNAL CONNECTIONS
TX_PE
TXD
TXCLK
TX_RDY
CCA
RESET
RXD
RXCLK
MD_RDY
RX_PE
CS
AS
R/W
SCLK
SD
2
3
4
5
32
28
35
36
34
33
9
23
8
24
25
BASEBAND
PROCESSOR
HFA3860B
PA_PE
TX_DATA
TXC
TX_RDY
CCA
RESET_BB
RADIO_PE
RXDATA
RXCIN
MD_RDY
RX_PE_BB
BB_CS
BB_AS
BB_RD/WR
CLK/SYNTH_CLK
SD/SYNTH_DATA
CLOCK
DATA
LE
11
12
13
SYNTHESIZER
HFA3524A
SYNTH_LE
LPF_TX_PE
MOD_TX_PE
LPF_RX_PE
MOD_RX_PE
LIM2_PE
LIM1_PE
22
41
21
43
54
74
MOD/DEMOD
HFA3726
TX_PE
RX_PE
TX_PE
RX_PE
15
28
UP/DOWN CONVERTER
HFA3624
HFA3925
POWER AMP
Application Note 9835
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