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參數資料
| 型號： | HX6218DBNC |
| 元件分類： | FIFO |
| 英文描述： | 2K X 18 OTHER FIFO, 30 ns, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 1/15頁 |
| 文件大小： | 717K |
| 代理商： | HX6218DBNC |
FIFO – HX6409/HX6218/HX6136
www.honeywell.com
1
The HX6409, HX6218, and HX6136 are high speed,
low power, first-in first-out memories with clocked read
and write interfaces. The HX6409 is a 4096-word by 9-
bit memory array; the HX6218 is a 2048-word by 18-bit
memory array; and the HX6136 is a 1024-word by 36-
bit memory array. The FIFOs support width expansion
while depth expansion requires external logic control
using state machine techniques. Features include
programmable parity control, an empty/full flag, a
quarter/three quarter full flag, a half full flag and an
error flag.
Honeywell’s FIFOs provide solutions for a wide variety
of data buffering needs, including high-speed data
acquisition, multiprocessor interfaces, and
communications buffering.
Input ports are controlled by a free running clock (CKW)
and a write-enable pin ENW. When ENW is asserted,
data is written into the FIFO on the rising edge of the
CKW signal. While ENW is held active, data is
continually written into the FIFO on each CKW cycle.
The output port is controlled in a similar manner by a
freerunning read clock (CKR) and a read enable pin
(ENR). In addition, the three FIFOs have an output
enable pin (OE) and a master reset pin (MR). The read
(CKR) and write (CKW) clocks may be tied together for
single-clock operation or the two clocks may be run
independently for asynchronous read/write applications.
Clock frequencies up to 28 MHz are achievable in the
three configurations.
Honeywell’s enhanced SOI RICMOS IV (Radiation
Insensitive CMOS) technology is radiation hardened
through the use of advanced and proprietary design,
layout and process hardening techniques. The FIFO is
fabricated with Honeywell’s radiation-hardened
technology, and is designed for use in systems
operating in radiation environments. The SOI
RICMOS IV process is a 5-volt, SOI CMOS
technology with a 150 gate oxide and a minimum
drawn feature size of 0.8m, (0.65m effective gate
length—Leff). Additional features include tungsten via
plugs, Honeywell’s proprietary SHARP planarization
process, and a lightly doped drain (LDD) structure.
1K x 36, 2K x 18, 4K x 9
configurations
Fabricated with RICMOS IV
Silicon on Insulator (SOI) 0.8
m process (Leff = 0.65m)
Total dose hardness through
1x10
6 rad(Si)
Neutron hardness through
1x10
14 cm-2
Dynamic and static transient
upset hardness through 1x10
9
rad(Si)/s
Dose rate survivability through
1x10
11 rad(Si)/s
Soft error rate of <1x10
-10
upsets/bit-day
No latchup
Read/write cycle times
36 ns (-55°to 125°C)
Expandable in Width
Empty, full, half full, 1/4 full,
full, error flags
Parity generation/checking
Fully asynchronous with
simultaneous read and write
operation
Output enable (OE)
CMOS or TTL compatible I/O
Single 5V ±10% power supply
Various flat pack options
FEATURES
First-In First-Out Memory
HX6409/HX6218/HX6136
相關PDF資料 |
PDF描述 |
|---|---|
| HX6228TBNC | 128K X 8 STANDARD SRAM, 25 ns, CDFP32 |
| HX6228TQHC | 128K X 8 STANDARD SRAM, 25 ns, CDFP32 |
| HX6228ASNT | 128K X 8 STANDARD SRAM, 25 ns, CDFP40 |
| HX6409TQHT | 4K X 9 OTHER FIFO, 30 ns, CDFP32 |
| HX80ML | 0.02 A, 8000 V, SILICON, SIGNAL DIODE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HX6218DBNT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DBRC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DBRT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DENC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| HX6218DENT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
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