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參數資料
| 型號： | HY29F080T-12 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | x8 Flash EEPROM |
| 中文描述： | 1M X 8 FLASH 5V PROM, 120 ns, PDSO40 |
| 封裝： | TSOP-40 |
| 文件頁數： | 5/38頁 |
| 文件大小： | 366K |
| 代理商： | HY29F080T-12 |
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5
Rev. 6.1/May 01
HY29F080
Table 1. HY29F080 Memory Array Organization
r
o
t
e
S
r
o
u
t
e
S
r
G
p
o
s
s
e
r
d
d
A
]
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
p
[
u
A
o
r
G
r
o
t
e
S
1
[
A
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
/
o
t
e
S
]
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
]
:
1
[
A
e
g
n
a
R
s
s
e
r
d
d
A
[
A
]
]
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
[
A
0
1
2
3
4
5
6
7
8
9
0
1
1
S
1
S
1
S
1
S
1
S
S
S
S
S
S
S
S
S
S
S
S
0
G
S
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
G
S
2
G
S
3
G
S
4
G
S
5
G
S
1
2
3
4
5
6
G
S
7
G
S
Notes:
1. A[19:16] are the sector address. A[19:17] are the sector group address.
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.
Table 2. HY29F080 Normal Bus Operations
1
n
o
r
e
p
O
#
E
C
#
E
O
#
E
W
#
T
E
S
E
R
]
:
1
[
A
]
:
[
Q
D
d
a
e
R
L
L
H
H
A
N
I
D
T
U
O
e
W
L
H
L
H
A
N
I
D
N
I
e
a
s
D
t
p
O
L
H
H
H
X
Z
-
g
y
b
d
n
a
S
L
T
T
#
E
C
H
X
X
H
X
Z
-
g
y
b
d
n
a
S
S
O
M
C
#
E
C
V
C
C
V
3
±
X
X
V
C
C
V
3
±
X
Z
-
g
)
b
d
n
a
S
L
T
T
(
t
s
e
R
e
r
w
d
r
H
X
X
X
L
X
Z
-
g
)
b
d
n
a
S
S
O
M
C
(
t
s
e
R
e
r
w
d
r
H
X
X
X
V
S
S
V
5
±
X
Z
-
g
Notes:
1. L = V
IL
, H = V
IH
, X = Don
’
t Care, D
OUT
= Data Out, D
IN
= Data In. See DC Characteristics for voltage levels.
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