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參數資料
| 型號： | HY29F400BG90 |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory |
| 中文描述： | 4兆位（512Kx8/256Kx16）5伏只閃存 |
| 文件頁數： | 16/40頁 |
| 文件大小： | 509K |
| 代理商： | HY29F400BG90 |
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16
Rev. 5.2/May 01
HY29F400
Table 6. Write and Erase Operation Status Summary
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Notes:
1. A valid address is required when reading status information. See text for additional information.
2. DQ[5] status switches to a
‘
1
’
when a program or erase operation exceeds the maximum timing limit.
3. A
‘
1
’
during sector erase indicates that the 50 μs time-out has expired and active erasure is in progress. DQ[3] is not
applicable to the chip erase operation.
4. Equivalent to
‘
No Toggle
’
because data is obtained in this state.
5. Programming can be done only in a non-suspended sector (a sector not marked for erasure).
rithm is in progress or completed, or whether the
device is in Erase Suspend mode. Data# Polling
is valid after the rising edge of the final WE# pulse
in the Program or Erase command sequence.
The system must do a read at the program ad-
dress to obtain valid programming status informa-
tion on this bit. While a programming operation is
in progress, the device outputs the complement
of the value programmed to DQ[7]. When the pro-
gramming operation is complete, the device out-
puts the value programmed to DQ[7]. If a pro-
gram operation is attempted within a protected
sector, Data# Polling on DQ[7] is active for ap-
proximately 2 μs, then the device returns to read-
ing array data.
The host must read at an address within any non-
protected sector scheduled for erasure to obtain
valid erase status information on DQ[7]. During
an erase operation, Data# Polling produces a
“
0
”
on DQ[7]. When the erase operation is complete,
or if the device enters the Erase Suspend mode,
Data# Polling produces a
“
1
”
on DQ[7]. If all sec-
tors selected for erasing are protected, Data#
Polling on DQ[7] is active for approximately 100
μs, then the device returns to reading array data.
If at least one selected sector is not protected, the
erase operation erases the unprotected sectors,
and ignores the command for the selected sec-
tors that are protected.
When the system detects that DQ[7] has changed
from the complement to true data (or
“
0
”
to
“
1
”
for
erase), it should do an additional read cycle to read
valid data from DQ[7:0]. This is because DQ[7]
may change asynchronously with respect to the
other data bits while Output Enable (OE#) is as-
serted low.
Figure 7 illustrates the Data# Polling test algorithm.
DQ[6] - Toggle Bit I
Toggle Bit I on DQ[6] indicates whether an Auto-
matic Program or Erase algorithm is in progress
or complete, or whether the device has entered
the Erase Suspend mode. Toggle Bit I may be
read at any address, and is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence, including during the sector
erase time-out. The system may use either OE#
or CE# to control the read cycles.
Successive read cycles at any address during an
Automatic Program algorithm operation (including
programming while in Erase Suspend mode)
cause DQ[6] to toggle. DQ[6] stops toggling when
the operation is complete. If a program address
falls within a protected sector, DQ[6] toggles for
approximately 2 μs after the program command
sequence is written, then returns to reading array
data.
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]
[
#
Q
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0
1
Q
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1
]
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[
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1
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1
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]
[
A
Q
N
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1
3
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]
[
A
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B
0
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4
2
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A
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5
#
Q
D
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1
a
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2
A
/
N
a
D
A
/
N
a
D
0
1
5
4
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