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參數(shù)資料
| 型號(hào)： | HY57V281620AT-SI |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4 Banks x 2M x 16bits Synchronous DRAM |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大小： | 81K |
| 代理商： | HY57V281620AT-SI |
HY57V281620A
4 Banks x 2M x 16bits Synchronous DRAM
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.4/Apr.01
DESCRIPTION
The Hynix HY57V281620A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require
low power consumption and extended temperature range . HY57V281620A is organized as 4banks of 2,097,152x16
HY57V281620A is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3
±
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM or LDQM
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable C A S Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V281620AT-KI
133MHz
Normal
4Banks x 2Mbits
x16
LVTTL
400mil 54pin TSOP II
H Y 5 7 V 2 8 1 6 2 0 A T - H I
133MHz
HY57V281620AT-PI
100MHz
HY57V281620AT-SI
100MHz
HY57V281620ALT-KI
133MHz
Low Power
H Y 5 7 V 2 8 1 6 2 0 A L T - H I
133MHz
HY57V281620ALT-PI
100MHz
HY57V281620ALT-SI
100MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V281620ALT-HI | 4 Banks x 2M x 16bits Synchronous DRAM |
| HY57V281620ALT-KI | 4 Banks x 2M x 16bits Synchronous DRAM |
| HY57V281620ELT-H | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT-5 | 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V281620BLT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx16|3.3V|4K|6/K/H/8/P/S|SDR SDRAM - 128M |
| HY57V281620BT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx16|3.3V|4K|6/K/H/8/P/S|SDR SDRAM - 128M |
| HY57V281620ELT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
| HY57V281620ELT-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O |
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