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參數資料
| 型號： | HY57V28820HCLT-8I |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4Banks x 4M x 8bits Synchronous DRAM |
| 中文描述： | 16M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 175K |
| 代理商： | HY57V28820HCLT-8I |
HY57V28820HC(L)T-I
4Banks x 4M x 8bits Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/Jan. 02 1
DESCRIPTION
The Hynix HY57V28820HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applica-
tions which require low power consumption and extended temperature range. f HY57V28820HC(L)T is organized as
4banks of 4,194,304x8.
HY57V28820HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
Single 3.3
±
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full Page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V28820HCT-6I
166MHz
Normal
4Banks x 4Mbits
x 8
LVTTL
400mil 54pin TSOP II
HY57V28820HCT-KI
133MHz
HY57V28820HCT-HI
133MHz
HY57V28820HCT-8I
125MHz
HY57V28820HCT-PI
100MHz
HY57V28820HCT-SI
100MHz
HY57V28820HCLT-6I
166MHz
Low power
HY57V28820HCLT-KI
133MHz
HY57V28820HCLT-HI
133MHz
HY57V28820HCLT-8I
125MHz
HY57V28820HCLT-PI
100MHz
HY57V28820HCLT-SI
100MHz
相關PDF資料 |
PDF描述 |
|---|---|
| HY57V28820HCLT-HI | 4Banks x 4M x 8bits Synchronous DRAM |
| HY57V28820HCLT-KI | 4Banks x 4M x 8bits Synchronous DRAM |
| HY57V28820HCLT-PI | 4Banks x 4M x 8bits Synchronous DRAM |
| HY57V28820HCLT-SI | 4Banks x 4M x 8bits Synchronous DRAM |
| HY57V28820HCT-6I | 4Banks x 4M x 8bits Synchronous DRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HY57V28820HCLT-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HY57V28820HCLT-HI | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 4M x 8bits Synchronous DRAM |
| HY57V28820HCLT-I | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 4M x 8bits Synchronous DRAM |
| HY57V28820HCLT-K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HY57V28820HCLT-KI | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 4M x 8bits Synchronous DRAM |
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