- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385420 > HY57V561620C (Hynix Semiconductor Inc.) 4 Banks x 4M x 16Bit Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | HY57V561620C |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 4 Banks x 4M x 16Bit Synchronous DRAM |
| 中文描述： | 4銀行x 4米× 16位同步DRAM |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 217K |
| 代理商： | HY57V561620C |
HY57V561620C(L)T(P)
4 Banks x 4M x 16Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.5 / June 2004 1
DESCRIPTION
The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16.
HY57V561620C(L)T(P) Series is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3
±
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch (Leaded Package or Lead Free Package)
All inputs and outputs referenced to positive edge of system
clock
Data mask function by UDQM, LDQM
Internal four banks operation
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Note :
1. HY57V561620CT Series : Nomal power & Leaded 54Pin TSOP II
2. HY57V561620CLT Series : Low power & Leaded 54Pin TSOP II
3. HY57V561620CTP Series : Nomal power & Lead Free 54Pin TSOP II
4. HY57V561620CLTP Series : Low power & Lead Free 54Pin TSOP II
Part No.
Clock Frequency
Power
Organization
Interface
400mil 54pin TSOP II
HY57V561620C(L)T(P)-6
166MHz
(Normal)
/
Low Power
4Banks x 4Mbits x16
LVTTL
(Leaded)
/
Lead Free
HY57V561620C(L)T(P)-7
143MHz
HY57V561620C(L)T(P)-K
133MHz
HY57V561620C(L)T(P)-H
133MHz
HY57V561620C(L)T(P)-8
125MHz
HY57V561620C(L)T(P)-P
100MHz
HY57V561620C(L)T(P)-S
100MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V561620CLT-6 | 4 Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620CLT-7 | 4 Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620CLT-H | 4 Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620CLT-K | 4 Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620CLT-P | 4 Banks x 4M x 16Bit Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V561620CLT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16Mx16|3.3V|8K|6/K/H/8/P/S|SDR SDRAM - 256M |
| HY57V561620CLT-6 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620CLT-7 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620CLT-8 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620CLT-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4 Banks x 4M x 16Bit Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。