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參數資料
| 型號： | HY5V56BLF-I |
| 英文描述： | 16Mx16|3.3V|8K|H/8/P/S|SDR SDRAM - 256M |
| 中文描述： | 16Mx16顯示| 3.3 | 8K的| H/8/P/S |特別提款權的SDRAM - 256M |
| 文件頁數： | 1/9頁 |
| 文件大小： | 236K |
| 代理商： | HY5V56BLF-I |
Preliminary
HY5V52CF
4 Banks x 2M x 32Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2/Jun 02
DESCRIPTION
The Hynix HY5V52CF is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications
which require wide data I/O and high bandwidth. HY5V52CF is organized as 4banks of 2,097,152x32.
HY5V52CF is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
90Ball FBGA with 0.8mm of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
ORDERING INFORMATION
Part No.
Clock Frequency
Organization
Interface
Package
HY5V52(L)F-8
125MHz
4Banks x 2Mbits
x32
LVTTL
90Ball FBGA
HY5V52(L)F-P
100MHz
4Banks x 2Mbits
x32
LVTTL
90Ball FBGA
HY5V52(L)F-S
100MHz
4Banks x 2Mbits
x32
LVTTL
90Ball FBGA
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