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參數(shù)資料
| 型號： | HY62QF8200SLM-70 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 8 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | MICRO, BGA-48 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 185K |
| 代理商： | HY62QF8200SLM-70 |
This document is a general product description and is subject to change without notice. Hyundai Electronics does not
assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.04 /Feb. 99
Hyundai Semiconductor
HY62UF8200/ HY62QF8200/ HY62EF8200/
HY62SF8200 Series 256Kx8bit full CMOS SRAM
DESCRIPTION
The HY62UF8200 / HY62QF8200 / HY62EF8200
/ HY62SF8200 is a high speed, super low power
and 2M bit full CMOS SRAM organized as
262,144 words by 8bits. The HY62UF8200 /
HY62QF8200 / HY62EF8200 / HY62SF8200 uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.5V.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup(LL/SL-part)
- 1.5V(min) data retention
Standard pin configuration
- 48ball uBGA
Product
Voltage
Speed
Operation
Standby Current(uA)
Temperature
No.
(V)
(ns)
Current(mA)
LL
SL
(
°C)
HY62UF8200
3.0
70/85/100
10
2
0~70(Normal)
HY62UF8200-I
3.0
70/85/100
10
2
-40~85(E.T.)
HY62QF8200
2.5
85/100/120
5
10
2
0~70(Normal)
HY62QF8200-I
2.5
85/100/120
5
10
2
-40~85(E.T.)
HY62EF8200
2.0
100/120/150
5
10
2
0~70(Normal)
HY62EF8200-I
2.0
100/120/150
5
10
2
-40~85(E.T.)
HY62SF8200
1.8
120/150/200
5
10
2
0~70(Normal)
HY62SF8200-I
1.8
120/150/200
5
10
2
-40~85(E.T.)
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
PIN CONNECTION ( Top View )
BLOCK DIAGRAM
A0
IO5
IO6
A1
CS2 A3
A6
A8
A2
/WE A4
A7
IO1
NC
A5
IO2
Vss
Vcc
Vss
IO7
NC
A17
IO3
IO8 /OE /CS1 A16 A15 IO4
A9
A10 A11 A12 A13 A14
PIN DESCRIPTION
Pin Name
Pin Function
Pin Name
Pin Function
/CS1
Chip Select 1
A0 ~ A17
Address Input
CS2
Chip Select 2
I/O1 ~ I/O8
Data Input/Output
/WE
Write Enable
Vcc
Power(3.0V, 2.5V, 2.0V or 1.8V)
/OE
Output Enable
Vss
Ground
/OE
A17
COLUMN
DECODER
A0
ROW DECODER
MEMORY ARRAY
2048x1024
SENSE
AMP
OUTPUT
BUFFER
I/O1
I/O8
ADD
INPUT
BUFFER
/CS1
CS2
/WE
WRITE
DRIVER
CONTROL
LOGIC
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