- 您現(xiàn)在的位置：買賣IC網 > PDF目錄370744 > HYB 39S256400T (SIEMENS AG) 256-Mbit(4banks × 16MBit × 4) Synchronous DRAM(256M(4列 × 16M位 × 4)同步動態(tài)RAM) PDF資料下載
參數資料
| 型號： | HYB 39S256400T |
| 廠商： | SIEMENS AG |
| 英文描述： | 256-Mbit(4banks × 16MBit × 4) Synchronous DRAM(256M(4列 × 16M位 × 4)同步動態(tài)RAM) |
| 中文描述： | 256兆位（4banks × 16兆× 4）同步DRAM（256M（4列× 1,600位× 4）同步動態(tài)RAM）的 |
| 文件頁數： | 1/47頁 |
| 文件大小： | 316K |
| 代理商： | HYB 39S256400T |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
HYB 39S256400/800/160T
256-MBit Synchronous DRAM
Data Book
1
12.99
The HYB 39S256400/800/160T are
4 banks
×
16MBit x4, 4 banks
×
8MBit x8 and 4 banks
×
4Mbit x16 respectively. These synchro-
nous devices achieve high speed data transfer rates for CAS-latencies by employing a chip
architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
The chip is fabricated using the Infineon advanced 256 MBit DRAM process technology.
four bank Synchronous DRAM’s organized as
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V
±
0.3 V power supply and are available in TSOPII packages.
High Performance:
Fully Synchronous to Positive Clock Edge
0 to 70
°
C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length: 1, 2, 4, 8
Multiple Burst Read with Single Write
Operation
Automatic and Controlled Precharge
Command
Data Mask for Read/Write Control (x4, x8)
Data Mask for Byte Control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
8192 Refresh Cycles / 64 ms (7.8
μ
s)
Random Column Address every CLK
(1-N Rule)
Single 3.3 V
±
0.3 V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
-7.5 parts for PC133 3-3-3 operation
-8
parts for PC100 2-2-2 operation
-8A
parts for PC100 3-2-2 operation
-8B
parts for PC100 3-2-3 operation
-7.5
-8
-8A
-8B
Units
f
CK
133
125
125
100
MHz
t
CK3
7.5
8
8
10
ns
t
AC3
5.4
6
6
6
ns
t
CK2
12
10
12
15
ns
t
AC2
6
6
6
7
ns
256-MBit Synchronous DRAM
相關PDF資料 |
PDF描述 |
|---|---|
| HYB 39S256800T | 256-Mbit(4banks × 8MBit × 8) Synchronous DRAM(256M(4列 × 8M位 × 8)同步動態(tài)RAM) |
| HYB 39S256400AT | 256-Mbit(4banks × 16MBit × 4) Synchronous DRAM(256M(4列 × 16M位 × 4)同步動態(tài)RAM) |
| HYB 39S256800AT | 256-Mbit(4banks × 8MBit × 8) Synchronous DRAM(256M(4列 × 8M位 × 8)同步動態(tài)RAM) |
| HYB 39S256160AT | 256-Mbit(4banks × 4MBit × 16) Synchronous DRAM(256M(4列 × 4M位 × 16)同步動態(tài)RAM) |
| HYB 39S256400CT | 256-Mbit(4banks × 16MBit × 4) Synchronous DRAM(256M(4列 × 16M位 × 4)同步動態(tài)RAM) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HYB39S256400T-10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 MBit Synchronous DRAM |
| HYB39S256400T-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HYB39S256400T-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 MBit Synchronous DRAM |
| HYB39S256400T-8B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 MBit Synchronous DRAM |
| HYB39S256402T-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。