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參數資料
| 型號： | HYB39S128400CT |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128-MBit Synchronous DRAM |
| 中文描述： | 128兆位同步DRAM |
| 文件頁數： | 1/51頁 |
| 文件大小： | 470K |
| 代理商： | HYB39S128400CT |
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HYB 39S128400/800/160CT(L)
128-MBit Synchronous DRAM
INFINEON Technologies
1
9.01
The HYB 39S128400/800/160CT are four bank Synchronous DRAM’s organized as 4
banks
×
8MBit x4, 4 banks
×
4MBit x8 and 4 banks
×
2Mbit x16 respectively. These synchronous
devices achieve high speed data transfer rates by employing a chip architecture that prefetches
multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using
the Infineon advanced 0.17 micron process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3 V
±
0.3 V power supply and are available in TSOPII packages.
High Performance:
Single Pulsed RAS Interface
Fully Synchronous to Positive Clock Edge
0 to 70
°
C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page
Multiple Burst Read with Single Write
Operation
Automatic and Controlled Precharge
Command
Data Mask for Read/Write Control (x4, x8)
Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
4096 Refresh Cycles / 64 ms
Random Column Address every CLK
(1-N Rule)
Single 3.3 V
±
0.3 V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPII-54 400mil x 875 mil width
(x4, x8, x16)
-7
for PC 133 2-2-2 applications
-7.5 for PC 133 3-3-3 applications
-8
for PC100 2-2-2 applications
-7
-7.5
-8
Units
f
CK
143
133
125
MHz
t
CK3
7
7.5
8
ns
t
AC3
5.4
5.4
6
ns
t
CK2
7.5
10
10
ns
t
AC2
5.4
6
6
ns
128-MBit Synchronous DRAM
相關PDF資料 |
PDF描述 |
|---|---|
| HYB39S128400CT-7 | 128-MBit Synchronous DRAM |
| HYB39S128400CT-75 | 128-MBit Synchronous DRAM |
| HYB39S128400CT-8 | 128-MBit Synchronous DRAM |
| HYB39S16160AT-10 | Multipole Connector |
| HYB39S16160CT-6 | 1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HYB39S128400CT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128-MBit Synchronous DRAM |
| HYB39S128400CT-7.5 | 制造商:Infineon Technologies AG 功能描述:32M X 4 SYNCHRONOUS DRAM, 5.4 NS, PDSO54 |
| HYB39S128400CT-75 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128-MBit Synchronous DRAM |
| HYB39S128400CT-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128-MBit Synchronous DRAM |
| HYB39S128400F | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:128-MBit Synchronous DRAM |
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