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參數資料
型號: ICS542MT
英文描述: Clock Divider
中文描述: 時鐘分頻器
文件頁數: 1/4頁
文件大小: 57K
代理商: ICS542MT
ICS542
Clock Divider
MDS 542 B
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126 (408) 295-9800tel www.icst.com
1
Revision 050400
Printed 11/14/00
Packaged as 8 pin SOIC
ICS’ lowest cost clock divider
Low skew (500ps) outputs. One is ÷ 2 of other.
Easy to use with other generators and buffers
Input clock frequency up to 156 MHz
Output clock duty cycle of 45/55
Power Down turns off chip
Output Enable
Advanced, low power CMOS process
Operating voltages of 3.0 to 5.5 V
The ICS542 is a cost effective way to produce a
high quality clock output divided from a clock
input. The chip accepts a clock input up to
156 MHz, and produces a divide by 2, 4, 6, 8, 12,
or 16 of the input clock. There are two outputs on
the chip, one being a low-skew divide by two of
the other. So, for instance, if a 100 MHz clock is
used, the ICS542 can produce low skew 50 MHz
and 25 MHz clocks, or low skew 25 MHz and
12.5 MHz clocks. The chip has an all-chip power
down mode that stops the outputs low, and an OE
pin that tri-states the outputs.
The ICS542 is a member of the ICS
ClockBlocks family of clock building blocks.
See the ICS541 and ICS543 for other clock
dividers, and the ICS501, 502, 511, 512 and 525
for clock multipliers.
Block Diagram
Description
Features
Divider and
Selection
Circuitry
VDD GND
CLK
Output
Buffer
Output
Buffer
S1, S0
2
÷2
Input Clock
OE (both outputs)
CLK/2
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