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參數(shù)資料
| 型號(hào)： | ICS615MT |
| 英文描述： | Set-Top Box Clock Source |
| 中文描述： | 機(jī)頂盒時(shí)鐘源 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 57K |
| 代理商： | ICS615MT |
ICS615
Set-Top Box Clock Source
MDS 615 A
Integrated Circuit Systems, Inc.525 Race StreetSan JoseCA95126(408)295-9800telwww.icst.com
1
Revision 052098
Printed 11/15/00
PRELIMINARY INFORMAT ION
ICRO
C
LOC K
Block Diagram
Description
Features
The ICS615 is a low cost, low jitter, high
performance PLL clock synthesizer designed to
replace 13.5, 27, and 54MHz crystals and
oscillators. Using analog/digital Phase-Locked
Loop (PLL) techniques, the device uses an
inexpensive external 13.5 MHz crystal or clock
input to produce output clocks of 13.5 MHz,
27 MHz, and 54 MHz .
ICS/MicroClock manufactures the largest variety
of Set-Top Box and multimedia clock synthesizers
for all applications. Our patented integrated
VCXO further reduces component count and cost
(see the MK2720). If more than three clock
outputs are needed, see the MK277x family of
parts. Consult ICS/MicroClock to eliminate
VCXOs, PLLs, crystals and oscillators from your
board.
Packaged in 8 pin narrow SOIC
Output clocks of 54, 27, and 13.5MHz
Uses a 13.500 MHz clock or external crystal
Full CMOS outputs with 25mA output drive
capability at TTL levels
Low skew outputs
Advanced, low power, sub-micron CMOS process
+3.3V or +5V operating voltage
See the MK2720 for these frequencies plus the
VCXO function, in an 8 pin SOIC.
Input
Buffer/
Crystal
Oscillator
PLL/Clock
Synthesis
Circuitry
13.5 MHz
Clock or
Crystal
X1
X2
Output
Buffer
54 MHz Clock
Output
Buffer
13.5 MHz Clock
Output
Buffer
27 MHz Clock
VDD
GND
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