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參數資料
| 型號： | ICS93701 |
| 英文描述： | DDR Phase Lock Loop Clock Driver |
| 中文描述： | 復員鎖相環時鐘驅動器 |
| 文件頁數： | 1/9頁 |
| 文件大小： | 184K |
| 代理商： | ICS93701 |
Integrated
Circuit
Systems, Inc.
ICS93701
0417B—10/29/02
Block Diagram
DDR Phase Lock Loop Clock Driver
Pin Configuration
48-Pin TSSOP
Recommended Application:
DDR Clock Driver
Product Description/Features:
Low skew, low jitter PLL clock driver
I
2
C for functional and output control
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Switching Characteristics:
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE - CYCLE jitter (66MHz):<120ps
CYCLE - CYCLE jitter (>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
DUTY CYCLE: 49.5% - 50.5%
Slew rate: 1V/ns - 2V/ns
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
SCLK
CLK_INT
CLK_INC
VDDI C
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
SDATA
FB_INC
FB_INT
VDD
FB_OUTT
FB_OUTC
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Functionality
S
T
U
N
P
N
I
I
K
S
T
T
T
U
U
O
P
T
B
U
F
O
e
L
L
P
D
D
V
m
o
V
m
o
V
m
o
V
A
5
n
5
n
5
n
T
L
C
C
N
I
K
L
C
T
K
L
C
C
K
L
C
_
C
T
U
O
_
B
F
)
L
H
L
H
L
H
n
o
)
H
L
H
L
H
L
n
o
)
)
H
M
0
2
<
)
Z
Z
Z
Z
f
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
SCLK
SDATA
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
相關PDF資料 |
PDF描述 |
|---|---|
| ICS93701YGT | DDR Phase Lock Loop Clock Driver |
| ICS93705 | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712YF-PPP-T | 2 DIMM DDR Fanout Buffer |
| ICS93712YF-T | 2 DIMM DDR Fanout Buffer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ICS93701YGT | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93705 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712 | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
| ICS93712YF-PPP-T | 制造商:ICS 制造商全稱:ICS 功能描述:2 DIMM DDR Fanout Buffer |
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