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參數資料
| 型號： | ICS94203 |
| 英文描述： | 18-Bit Universal Bus Transceivers With 3-State Outputs 56-SSOP -40 to 85 |
| 中文描述： | 可編程系統頻率發生器有價證券/三⑩ |
| 文件頁數： | 1/18頁 |
| 文件大小： | 183K |
| 代理商： | ICS94203 |
Integrated
Circuit
Systems, Inc.
ICS94203
94203 Rev B 02/13/01
Pin Configuration
Recommended Application:
810/810E and Solano (815) type chipset
Output Features:
2 - CPUs @ 2.5V
13 - SDRAM @ 3.3V
3 - 3V66 @ 3.3V
7 - PCI @3.3V
1 - 24/48MHz@ 3.3V
1 - 48MHz @ 3.3V fixed
1 - REF @3.3V, 14.318MHz
Features:
Programmable ouput frequency
Gear ratio change detection
Real time system reset output
Spread spectrum for EMI control
with programmable spread percentage
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Support power management through PD#.
Uses external 14.318MHz crystal
FS pins for frequency select
Key Specifications:
CPU Output Jitter: <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
CPU Output Skew: <175ps
PCI Output Skew: <500ps
3V66 Output Skew <175ps
For group skew timing, please refer to the
Group Timing Relationship Table.
Programmable System Frequency Generator for P
II
/
III
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
VDDA
GNDA
X1
X2
GND3V66
VDD3V66
3V66-0
3V66-1
3V66-2
VDDPCI
GNDPCI
*FS0/PCICLK0
*FS1/PCICLK1
*SEL24_48#/PCICLK2
GNDPCI
VDDPCI
PCICLK3
PCICLK4
PCICLK5
PCICLK6
RATIO_0
PD#
SCLK
SDATA
VDD48
GND48
*FS2/24_48MHz
*FS3/48MHz
1
1
1
REF/FS4*
VDDLAPIC
IOAPIC0
VDDLCPU
GNDLCPU
CPUCLK0
CPUCLK1
GNDSDR
VDDSDR
SDRAM0
SDRAM1
SDRAM2
SDRAM3
VDDSDR
GNDSDR
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM_F
GNDSDR
VDDSDR
SDRAM8
SDRAM9
SDRAM10
SDRAM11
RESET#
RATIO_1
1
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Block Diagram
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (1:0)
2
12
7
3
SDRAM (11:0)
IOAPIC
PCICLK (6:0)
SDRAM_F
3V66 (2:0)
RESET#
RATIO_0
RATIO_1
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
FS(4:0)
PD#
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
/ 2
REF
Power Groups
VDDA, GNDA = Core PLL, Xtal
VDD48, GND48 = 48MHz, Fixed PLL
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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