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參數資料
| 型號： | IDT2308A-2HPG |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V ZERO DELAY CLOCK MULTIPLIER |
| 中文描述： | 3.3零延遲時鐘倍頻 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 79K |
| 代理商： | IDT2308A-2HPG |
1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK
MULTIPLIER
IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
J ULY 2004
2004 Integrated Device Technology, Inc.
DSC 6587/8
c
COMMERCIAL AND INDUS T RIAL T EMPERAT URE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
Distributes one clock input to two banks of four outputs
Separate output enable for each output bank
External feedback (FBK) pin is used to synchronize the outputs
to the clock input
Output Skew <200 ps
Low jitter <200 ps cycle-to-cycle
1x, 2x, 4x output options (see table):
– IDT2308A-1 1x
– IDT2308A-2 1x, 2x
– IDT2308A-3 2x, 4x
– IDT2308A-4 2x
– IDT2308A-1H and -2H for High Drive
No external RC network required
Operates at 3.3V V
DD
Available in SOIC and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is
designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incomng
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT2308A has two banks of four outputs each that are controlled via two
select addresses. By proper selection of input addresses, both banks can be
put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for systemtesting purposes. In the absence of an
input clock, the IDT2308A enters power down. In this mode, the device will
draw less than 12μA for Commercial Temperature range and less than 25μA
for Industrial temperature range, and the outputs are tri-stated.
The IDT2308A is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT2308A is characterized for both Industrial and Commercial opera-
tion.
IDT2308A
PLL
S1
2
14
15
3
CLKA1
CLKA2
CLKA3
CLKA4
6
10
11
CLKB1
CLKB2
CLKB3
CLKB4
9
FBK
16
Control
Logic
7
8
1
REF
S2
(-2, -3)
(-3, -4)
2
2
相關PDF資料 |
PDF描述 |
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| IDT2308A-2HPGG | 3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2HPGGI | 3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2HPGI | 3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2PG | 3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2PGG | 3.3V ZERO DELAY CLOCK MULTIPLIER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| IDT2308A-2HPGG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2HPGGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2HPGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2PG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V ZERO DELAY CLOCK MULTIPLIER |
| IDT2308A-2PGG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V ZERO DELAY CLOCK MULTIPLIER |
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