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參數(shù)資料
| 型號： | IDT5V9950PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Scan Test Devices With 18-Bit Bus Transceivers And Registers 64-LQFP -40 to 85 |
| 中文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 67K |
| 代理商： | IDT5V9950PFI |
1
INDUSTRIAL TEMPERATURE RANGE
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
FEBRUARY 2002
2002 Integrated Device Technology, Inc.
DSC 5870/4
c
INDUS T RIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Ref input is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency: 6MHz to 200MHz
Output frequency: 6MHz to 200MHz
2x, 4x, 1/2, and 1/4 outputs
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Available in TQFP package
FUNCTIONAL BLOCK DIAGRAM
sOE
1Q
0
Skew
Select
1Q
1
1F1:0
3
3
2Q
0
Skew
Select
2Q
1
2F1:0
FS
3
REF
PLL
FB
3
3
3Q
0
Skew
Select
3Q
1
3F1:0
3
3
4Q
0
4Q
1
Skew
Select
4F1:0
3
3
PE TEST
3
IDT5V9950
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK II JR.
DESCRIPTION:
The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V9950 has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals that
may be hard-wired to appropriate HIGH-MID-LOW levels.
When the
sOE
pin is held low, all the outputs are synchronously enabled.
However, if
sOE
is held high, all the outputs except 2Q0 and 2Q1 are
synchronously disabled.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF. The IDT5V9950 has
LVTTL outputs with 12mA balanced drive outputs.
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| IDT5V9955BFGI | 功能描述:IC CLK DVR PLL 3.3 PROGR 96FBGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ W 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| IDT5V9955BFGI8 | 功能描述:IC CLK DVR PLL 3.3 PROGR 96FBGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ W 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| IDT5V9955BFI | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT5V995PFGI | 功能描述:IC CLK DVR PLL 3.3V PROGR 44TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ II 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| IDT5V995PFGI8 | 功能描述:IC CLK DVR PLL 3.3V PROGR 44TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ II 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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