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參數資料
| 型號： | IDTCSPU877A |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| 中文描述： | 1.8鎖相環微分1:10 SDRAM的時鐘驅動器 |
| 文件頁數： | 1/13頁 |
| 文件大?。?/td> | 139K |
| 代理商： | IDTCSPU877A |
1
IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
Y0
Y0
FBOUT
Y1
Y1
Y5
Y5
Y4
Y4
Y3
Y3
Y2
Y2
Y8
Y8
Y6
Y6
Y7
Y7
Y9
Y9
FBOUT
FBIN
FBIN
PLL
CLK
CLK
POWER
DOWN
AND
TEST
MODE
LOGIC
LD
AV
DD
OE
OS
LD or OE
LD, OS, or OE
PLL BYPASS
10K
- 100K
2004 Integrated Device Technology, Inc.
DSC-6495/4
c
IDTCSPU877A
COMME RCIAL T E MPE RAT URE RANGE
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
J ANUARY 2004
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
1 to 10 differential clock distribution
Optimized for clock distribution in DDR2 (Double Data Rate)
SDRAMapplications
Operating frequency: 125MHz to 270MHz
Very low skew:
≤
40ps
Very low jitter:
≤
40ps
1.8V AV
DD
and 1.8V V
DDQ
CMOS control signal input
Test mode enables buffers while disabling PLL
Low current power-down mode
Tolerant of Spread Spectrum input clock
Available in 52-Ball VFBGA and 40-pin MLF packages
FUNCTIONAL BLOCK DIAGRAM
NOTE:
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and
CLK
.
DESCRIPTION:
The CSPU877A is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK,
CLK
) to 10 differential
output pairs (Y
[0:9]
,
Y
[0:9]
) and one differential pair of feedback clock output
(FBOUT,
FBOUT
). External feedback pins (FBIN,
FBIN
) for synchronization
of the outputs to the input reference is provided. OE, OS, and A
VDD
control the
power-down and test mode logic. When A
VDD
is grounded, the PLL is turned
off and bypassed for test mode purposes. When the differential clock inputs
(CLK,
CLK
) are both at logic low, this device will enter a low power-down mode.
In this mode, the receivers are disabled, the PLL is turned off, and the output
clock drivers are disabled, resulting in a current consumption device of less than
500
μ
A.
The CSPU877A requires no external components and has been optimsed
for very low phase error, skew, and jitter, while maintaining frequency and duty
cycle over the operating voltage and temperature range. The CSPU877A,
designed for use in both module assemblies and systemmotherboard based
solutions, provides an optimumhigh-performance clock source.
The CSPU877A is available in Commercial Temperature Range (0
°
C to
+70
°
C). See Ordering Information for details.
APPLICATIONS:
Meets or exceeds JEDEC standard 82.8 for registered DDR2
clock driver
Along with SSTU32864/65/66, DDR2 register, provides complete
solution for DDR2 DIMMs
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IDTCSPU877ABV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPU877ABVG | 功能描述:IC SDRAM CLK DVR 1:10 52-VFBGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| IDTCSPU877ABVG8 | 功能描述:IC PLL CLK DVR SDRAM 56-CABGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| IDTCSPU877ANL | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPU877ANLG | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數:1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
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