- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄360984 > IS42S16800A-7B 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | IS42S16800A-7B |
| 英文描述： | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 中文描述： | 16Meg × 8，8Meg x16 |
| 文件頁(yè)數(shù)： | 31/66頁(yè) |
| 文件大小： | 556K |
| 代理商： | IS42S16800A-7B |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)當(dāng)前第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION
Rev. 00A
06/01/02
31
ISSI
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ
NOP
NOP
NOP
CAS Latency - 3
t
AC
t
OH
D
OUT
T0
T1
T2
T3
T4
t
LZ
CLK
COMMAND
DQ
READ
NOP
NOP
CAS Latency - 2
t
AC
t
OH
D
OUT
T0
T1
T2
T3
t
LZ
CAS LATENCY
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and the
latency is
m
clocks, the data will be available by clock edge
n +
m. The DQs will start driving as a result of the clock edge
one cycle earlier
(n + m
- 1), and provided that the relevant
access times are met, the data will be valid by clock edge
n +
m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a READ
command is registered at T0 and the latency is programmed
to two clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in CAS Latency diagrams. The
Allowable Operating Frequency table indicates the operat-
ing frequencies at which each CAS latency setting can be
used.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
7.5
100
133
10
75
100
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42S16800A-7BI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-7T | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-7TI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-10T | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-10TI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S16800A-7BI | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-7BL | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S16800A-7T | 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-7TI | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S16800A-7TL | 制造商:Integrated Silicon Solution Inc 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。