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參數(shù)資料
型號(hào)： IS42S32400A-10TLI
廠商： INTEGRATED SILICON SOLUTION INC
元件分類： DRAM
英文描述： 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
中文描述： 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO86
封裝： LEAD FREE, PLASTIC, TSOP2-86
文件頁(yè)數(shù)： 19/66頁(yè)
文件大小： 556K
代理商： IS42S32400A-10TLI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION
Rev. 00A
06/01/02
19
ISSI
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
DC ELECTRICAL CHARACTERISTICS
(Recommended Operation Conditions unless otherwise noted.)
Symbol
I
IL
Parameter
Input Leakage Current
Test Condition
0V
≤
V
IN
≤
V
DD
, with pins other than
the tested pin at 0V
Output s disabled, 0V
≤
V
OUT
≤
V
DD
I
OUT
= –2 mA
I
OUT
= +2 mA
One Bank Operation,
Burst Length=1
t
RC
≥
t
RC
(min.)
I
OUT
= 0mA
Speed
Min.
–5
Max.
5
Unit
μA
I
OL
V
OH
V
OL
I
DD1
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Operating Current
(1,2)
–5
2.4
—
5
—
0.4
μA
V
V
CAS
atency = 3
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
-7
-7
-10
-10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
120
140
110
120
1
1
.6
.6
11
5
7
4
6
3
5
28
17
20
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
I
DD2P
Precharge Standby Current
CKE
≤
V
IL
(
MAX
)
t
CK
= t
CK
(
MIN
)
I
DD2PS
(In Power-Down Mode)
t
CK
=
∞
I
DD2N
I
DD2NS
Precharge Standby Current
(In Non Power-Down Mode)
CKE
≥
V
IH
(
MIN
)
t
CK
= t
CK
(
MIN
)
t
CK
=
∞
Com.
Ind.
Com.
Ind.
Com.
Ind.
I
DD3P
Active Standby Current
CKE
≤
V
IL
(
MAX
)
t
CK
= t
CK
(
MIN
)
Ind.
t
CK
=
∞
I
DD3PS
(In Power-Down Mode)
I
DD3N
I
DD3NS
Active Standby Current
(In Non Power-Down Mode)
CKE
≥
V
IH
(
MIN
)
t
CK
= t
CK
(
MIN
)
t
CK
=
∞
Com.
Ind.
I
DD4
Operating Current
(In Burst Mode)
(1)
t
CK
= t
CK
(
MIN
)
I
OUT
= 0mA
CAS
atency = 3
Com.
Ind.
Com.
Ind.
-7
-7
-10
-10
—
—
—
—
120
140
110
120
mA
mA
mA
mA
CAS
atency = 2
Com.
Ind.
Com.
Ind.
-7
-7
-10
-10
—
—
—
—
90
110
80
100
mA
mA
mA
mA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time
increases. Also note that a bypass capacitor of at least 0.01 μF should be inserted between Vdd and Vss for each memory
chip to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. Idd
1
and Idd
4
depend on the output load. The maximum values for Idd
1
and Idd
4
are obtained with the output open state.
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