- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360984 > IS42S32400A-7B 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | IS42S32400A-7B |
| 英文描述： | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 中文描述： | 16Meg × 8，8Meg x16 |
| 文件頁數(shù)： | 33/66頁 |
| 文件大小： | 556K |
| 代理商： | IS42S32400A-7B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION
Rev. 00A
06/01/02
33
ISSI
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
CLK
CKE
HIGH
COLUMN ADDRESS
AUTO PRECHARGE
NO PRECHARGE
CS
RAS
CAS
WE
A0-A7
A10
BA0, BA1
BANK ADDRESS
A8, A9, A11
READ COMMAND
READS
READ bursts are initiated with a READ command, as shown
in the READ COMMAND diagram.
The starting column and bank addresses are provided with the
READ command, and auto precharge is either enabled or
disabled for that burst access. If auto precharge s enabled, the
row being accessed is precharged at the completion of the
burst. For the generic READ commands used in the following
illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the
starting column address will be available following the CAS
latency after the READ command. Each subsequent data-
out element will be valid by the next positive clock edge. The
CAS Latency diagram shows general timing
for each possible CAS latency setting.
Upon completion of a burst, assuming no other commands
have been initiated, the DQs will go High-Z. A full-page burst
will continue until terminated. (At the end of the page, it will
wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subse-
quent READ command, and data from a fixed-length READ
burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be
maintained. The first data element from the new burst follows
either the last element of a completed burst or the last desired
data element of a longer burst which is being truncated.
The new READ command should be issued
x
cycles before
the clock edge at which the last desired data element is
valid, where
x
equals the CAS latency minus one. This is
shown in Consecutive READ Bursts for CAS latencies of
two and three; data element
n
+ 3 is either the last of a burst
of four or the last desired of a longer burst. The 64Mb
SDRAM uses a pipelined architecture and therefore does
not require the
2n
rule associated with a prefetch architec-
ture. A READ command can be initiated on any clock cycle
following a previous READ command. Full-speed random
read accesses can be performed to the same bank, as shown
in Random READ Accesses, or each subsequent READ
may be performed to a different bank.
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-length
READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations).
The WRITE burst may be initiated on the clock edge
immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be
avoided. In a given system design, there may be a possi-
bility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a
single-cycle delay should occur between the last read data
and the WRITE command.
The DQM input is used to avoid I/O contention, as shown
in Figures RW1 and RW2. The DQM signal must be
asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers) to
suppress data-out from the READ. Once the WRITE com-
mand is registered, the DQs will go High-Z (or remain High-
Z), regardless of the state of the DQM signal, provided the
DQM was active on the clock just prior to the WRITE
command that truncated the READ command. If not, the
second WRITE will be an invalid WRITE. For example, if
DQM was LOW during T4 in Figure RW2, then the WRITEs
at T5 and T7 would be valid, while the WRITE at T6 would
be invalid.
The DQM signal must be de-asserted prior to the WRITE
command (DQM latency is zero clocks for input buffers) to
ensure that the written data is not masked. Figure RW1
shows the case where the clock frequency allows for bus
contention to be avoided without adding a NOP cycle, and
Figure RW2 shows the case where the additional NOP is
needed.
A fixed-length READ burst may be followed by, or truncated
with, a
PRECHARGE
command to the same bank
(provided
that auto precharge was not activated)
, and a full-page burst
may be truncated with a PRECHARGE command to the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS42S32400A-7BI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-7T | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-7TI | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A-10B | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42LS32400A | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS42S32400A-7BI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-7BL | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS42S32400A-7T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-7TI | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| IS42S32400A-7TL | 制造商:Integrated Silicon Solution Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。