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參數(shù)資料
型號(hào)： IS42S32400A-7TI
廠商： INTEGRATED SILICON SOLUTION INC
元件分類(lèi)： DRAM
英文描述： 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
中文描述： 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PDSO86
封裝： PLASTIC, TSOP2-86
文件頁(yè)數(shù)： 55/66頁(yè)
文件大小： 556K
代理商： IS42S32400A-7TI
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
ADVANCED INFORMATION
Rev. 00A
06/01/02
55
ISSI
IS42S81600A, IS42S16800A, IS42S32400A
IS42LS81600A, IS42LS16800A, IS42LS32400A
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
NOP
D
OUT
a
D
OUT
a+1
D
OUT
b
D
OUT
b+1
COL a
BCOL b
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
t
RP - BANK n
t
RP - BANK m
RBANK n
BANK m
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Idle
Page Active
READ with Burst of 4
Precharge
Internal States
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQM
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
NOP
D
OUT
a
D
IN
b
D
IN
b+1
D
IN
b+2
D
IN
b+3
COL a
BCOL b
CAS Latency - 3 (BANK n)
t
RP - BANK n
t
RP - BANK m
WRITE - AP
BANK n
WRITE - AP
BANK m
READ with Burst of 4
Interrupt Burst, Precharge
Idle
Page Active
WRITE with Burst of 4
Write-Back
Internal States
Page Active
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit
(M9)
in the mode register to a logic 1.
In this mode, all
WRITE
commands result in the access of a
single column location (burst of one), regardless of the
programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE.
ISSI
SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a READ on bank n, CAS
latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered.
2. Interrupted by a WRITE (with or without auto precharge):
A WRITE to bank m will interrupt a READ on bank n when
registered. DQM should be used two clocks prior to the
WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
READ With Auto Precharge interrupted by a READ
READ With Auto Precharge interrupted by a WRITE
相關(guān)PDF資料
PDF描述
IS42S32400A-7TL 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS61C256AH-8J x8 SRAM
IS61C256AH-8N x8 SRAM
IS61C256AH-8T x8 SRAM
IS61M256-10J x8 SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS42S32400A-7TL 制造商:Integrated Silicon Solution Inc 功能描述:
IS42S32400A-7TLI 制造商:Integrated Silicon Solution Inc 功能描述:
IS42S32400B 制造商:ISSI 制造商全稱(chēng):Integrated Silicon Solution, Inc 功能描述:4Meg x 32 128-MBIT SYNCHRONOUS DRAM
IS42S32400B-6B 制造商:Integrated Silicon Solution Inc 功能描述:IC SDRAM 128MBIT 166MHZ 90FBGA
IS42S32400B-6BL 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 4Mx32 166Mhz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問(wèn)時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube
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