- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360988 > IS61LV6432-117PQ 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM PDF資料下載
參數(shù)資料
| 型號： | IS61LV6432-117PQ |
| 英文描述： | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| 中文描述： | 64K的× 32 SYNCHRONOU擰管道靜態(tài)RAM |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 487K |
| 代理商： | IS61LV6432-117PQ |
IS61LV6432
14
Integrated Circuit Solution Inc.
SSR005-0B
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS
(Over Operating Range)
-166
Min. Max
-133
-117
-5
-6
-7
-8
Symbol Parameter
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Min.Max.
Unit
t
KC
Cycle Time
6
—
7.5
—
8.5
—
10
—
12
—
13
—
15
—
ns
t
KH
Clock High Time
2.4
—
2.8
—
3.0
—
3.5
—
4
—
6
—
6
—
ns
t
KL
Clock Low Time
2.4
—
2.8
—
3.0
—
3.5
—
4
—
6
—
6
—
ns
t
KQ
Clock Access Time
—
5
—
5
—
5
—
5
—
6
—
7
—
8
ns
t
KQX
(4)
Clock High to Output Invalid
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
2
—
2
—
ns
t
KQLZ
(4,5)
Clock High to Output Low-Z
0
—
0
—
0
—
0
—
0
—
0
—
0
—
ns
t
KQHZ
(4,5)
Clock High to Output High-Z
1.5
5
1.5
5
1.5
6
1.5
6
1.5
6
2
6
2
6
ns
t
OEQ
Output Enable to Output Valid
—
5
—
5
—
5
—
5
—
6
—
6
—
6
ns
t
OEQX
(4)
Output Disable to Output Invalid
0
—
0
—
0
—
0
—
0
—
0
—
0
—
ns
t
OELZ
(4,5)
Output Enable to Output Low-Z
0
—
0
—
0
—
0
—
0
—
0
—
0
—
ns
t
OEHZ
(4,5)
Output Disable to Output High-Z
—
3
—
3
—
4
—
4
—
5
—
6
—
6
ns
t
AS
Address Setup Time
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
SS
Address Status Setup Time
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
CES
Chip Enable Setup Time
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
AH
Address Hold Time
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
SH
Address Status Hold Time
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
CEH
Chip Enable Hold Time
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
ZZS
ZZ Standby
(1)
2
—
2
—
2
—
2
—
2
—
2
—
2
—
cyc
t
ZZREC
ZZ Recovery
(2)
2
—
2
—
2
—
2
—
2
—
2
—
2
—
cyc
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2.
ADSC
and
ADSP
must not be asserted for at least 2 cyc after leaving ZZ state.
3. Configuration signal MODE is static and must not change during normal operation.
4. Guaranteed but not 100% tested. This parameter is periodically sampled.
5. Tested with load in Figure 2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61LV6432-117PQI | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432 | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-117TQ | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-8PQI | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61NW6432 | 64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61LV6432-117PQI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-117TQ | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-117TQI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-133PQ | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-133TQ | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。