欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號(hào): IS61LV6432
英文描述: 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
中文描述: 64K的× 32 SYNCHRONOU擰管道靜態(tài)RAM
文件頁(yè)數(shù): 1/16頁(yè)
文件大小: 487K
代理商: IS61LV6432
IS61LV6432
IS61LV6432
64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM
Integrated Circuit Solution Inc.
1
SSR005-0B
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Pentium or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
Power-down control by ZZ input
JEDEC 100-Pin LQFP and PQFP package
3.3V V
CC
and 2.5V V
CCQ
for 2.5 I/O's
Two Clock enables and one Clock disable to
eliminate multiple bank bus contention.
Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
Q
or V
CCQ
to alter their power-up state
Industrial temperature available
DESCRIPTION
The
ICSI
IS61LV6432 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the Pentium, 680X0, and
PowerPC microprocessors. It is organized as 65,536 words
by 32 bits, fabricated with
ICSI
's advanced CMOS technology.
The device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQ1-DQ8,
BW2
controls DQ9-DQ16,
BW3
controls DQ17-DQ24,
BW4
controls DQ25-DQ32, conditioned
by
BWE
being LOW. A LOW on
GW
input would cause all bytes
to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61LV6432 and controlled by the
ADV
(burst address
advance) input pin.
Asynchronous signals include output enable (
OE
), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GND
Q
, on MODE pin selects LINEAR Burst. A V
CCQ
(or no connect) on MODE pin selects INTERLEAVED Burst.
FAST ACCESS TIME
Symbol
Parameter
-166
-133
-117
-5
-6
-7
-8
Unit
t
KQ
CLK Access Time
5
5
5
5
6
7
8
ns
t
KC
Cycle Time
6
7.5
8.5
10
12
13
15
ns
Frequency
166
133
117
100
83
75
66
MHz
相關(guān)PDF資料
PDF描述
IS61LV6432-117TQ 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-8PQI 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61NW6432 64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
IS61NW6432-5PQ 64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
IS61NW6432-5TQ 64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS61LV6432-117PQ 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-117PQI 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-117TQ 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-117TQI 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
IS61LV6432-133PQ 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
主站蜘蛛池模板: 隆回县| 达日县| 禄丰县| 高邑县| 湟源县| 七台河市| 平阳县| 霍山县| 富蕴县| 札达县| 上杭县| 镇赉县| 沙雅县| 濉溪县| 鸡西市| 太保市| 贵州省| 安塞县| 林口县| 南昌县| 县级市| 马鞍山市| 建平县| 甘孜县| 阜平县| 清苑县| 铜山县| 辽源市| 双辽市| 苏尼特右旗| 武强县| 晋城| 收藏| 花莲县| 子洲县| 虞城县| 兴安盟| 班玛县| 潜山县| 武定县| 太湖县|